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audio codec for recordable dvd adav803 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2007 analog devices, inc. all rights reserved. features stereo analog-to-digital converter (adc) supports 48 khz/96 khz sample rates 102 db dynamic range single-ended input automatic level control stereo digital-to-analog converter (dac) supports 32 khz/44.1 khz/48 khz/96 khz/192 khz sample rates 101 db dynamic range single-ended output asynchronous operation of adc and dac stereo sample rate converter (src) input/output range: 8 khz to 192 khz 140 db dynamic range digital interfaces record playback auxiliary record auxiliary playback s/pdif (iec 60958) input and output digital interface receiver (dir) digital interface transmitter (dit) pll-based audio mclk generators generates required dvdr system mclks device control via i 2 c-compatible serial port 64-lead lqfp package functional block diagram analog-to-digital converter reference src digital-to-analog converter adav803 dit aux data output record data output control registers pll digital input/output switching matrix (data path) playback data input aux data input dir vinl vinr vref voutr filtd iauxlrclk iauxbclk iauxsdata dirin olrclk obclk osdata oauxlrclk oauxbclk oauxsdata ditout sda scl ad0 ad1 sysclk3 sysclk2 sysclk1 zerol/int zeror mclki xout xin mclko voutl 04756-001 ilrclk ibclk isdata figure 1. applications dvd-recordable all formats cd-r/w general description the adav803 is a stereo audio codec intended for applications such as dvd or cd recorders that require high performance and flexible, cost-effective playback and record functionality. the adav803 features analog devices, inc. proprietary, high performance converter cores to provide record (adc), playback (dac), and format conversion (src) on a single chip. the adav803 record channel features variable input gain to allow for adjustment of recorded input levels and automatic level control, followed by a high performance stereo adc whose digital output is sent to the record interface. the record channel also features level detectors that can be used in feedback loops to adjust input levels for optimum recording. the playback channel features a high performance stereo dac with independent digital volume control. the sample rate converter (src) provides high performance sample rate conversion to allow inputs and outputs that require different sample rates to be matched. the src input can be selected from playback, auxiliary, dir, or adc (record). the src output can be applied to the playback dac, both main and auxiliary record channels, and a dit. operation of the adav803 is controlled via an i 2 c?-compatible serial interface, which allows the programming of individual control register settings. the adav803 operates from a single analog 3.3 v power supply and a digital power supply of 3.3 v with an optional digital interface range of 3.0 v to 3.6 v. the part is housed in a 64-lead lqfp package and is character- ized for operation over the commercial temperature range of ?40c to +85c.
adav803* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? adav803 evaluation board documentation application notes ? an-910: recovering the dir pll operation on the adav801 and adav803 data sheet ? adav803: audio codec for recordable dvd data sheet software and systems requirements ? adav80x sound codec linux driver reference designs ? cn0219 reference materials technical articles ? benchmarking integrated audio: why cpu usage alone no longer predicts user experience design resources ? adav803 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all adav803 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
adav803 rev. a | page 2 of 60 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 test conditions............................................................................. 3 adav803 specifications ............................................................. 3 timing specifications .................................................................. 7 temperature range ...................................................................... 7 absolute maximum ratings............................................................ 8 esd caution.................................................................................. 8 pin configuration and function descriptions............................. 9 typical performance characteristics ........................................... 11 functional description .................................................................. 15 adc section ............................................................................... 15 dac section................................................................................ 18 sample rate converter (src) functional overview ............ 19 pll section ................................................................................. 22 s/pdif transmitter and receiver ............................................ 23 serial data ports ......................................................................... 27 interface control ............................................................................ 30 i 2 c interface ................................................................................ 30 block reads and writes ............................................................. 31 register descriptions ..................................................................... 32 layout considerations................................................................... 59 adc ............................................................................................. 59 dac.............................................................................................. 59 pll ............................................................................................... 59 reset and power-down considerations ................................. 59 outline dimensions ....................................................................... 60 ordering guide .......................................................................... 60 revision history 7/07rev. 0 to rev. a changes to table 1............................................................................ 3 changes to adc section............................................................... 15 changes to figure 25...................................................................... 15 changes to figure 33...................................................................... 21 changes to src architecture section ......................................... 21 changes to table 7.......................................................................... 22 changes to figure 36...................................................................... 22 changes to figure 39, figure 40, figure 41, figure 42 .............. 23 changes to transmitter operation section ................................ 27 changes to interrupts section ...................................................... 27 changes to figure 50...................................................................... 28 changes to table 97........................................................................ 47 changes to table 101...................................................................... 48 changes to table 136 and table 137 ............................................ 56 updated outline dimensions ....................................................... 60 changes to ordering guide .......................................................... 60 7/04revision 0: initial version
adav803 rev. a | page 3 of 60 specifications test conditions test conditions, unless otherwise noted. table 1. test parameter condition supply voltage analog 3.3 v digital 3.3 v ambient temperature 25c master clock (mclki) 12.288 mhz measurement bandwidth 20 hz to 20 khz word width (all converters) 24 bits load capacitance on digital outputs 100 pf adc input frequency 1007.8125 hz at ?1 dbfs dac output frequency 960.9673 hz at 0 dbfs digital input slave mode, i 2 s justified format digital output slave mode, i 2 s justified format adav803 specifications table 2. parameter min typ max unit comments pga section input impedance 4 k minimum gain 0 db maximum gain 24 db gain step 0.5 db reference section absolute voltage, v ref 1.5 v v ref temperature coefficient 80 ppm/c adc section number of channels 2 resolution 24 bits dynamic range ?60 db input unweighted 99 db f s = 48 khz 98 db f s = 96 khz a-weighted 98 102 db f s = 48 khz 101 db f s = 96 khz total harmonic distortion + noise input = ?1.0 dbfs ?88 db f s = 48 khz ?87 db f s = 96 khz analog input input range ( full scale) 1.0 v rms dc accuracy gain error ?1.5 ?0.8 db interchannel gain mismatch 0.05 db gain drift 1 mdb/c offset ?10 mv
adav803 rev. a | page 4 of 60 parameter min typ max unit comments crosstalk (eiaj method) ?110 db volume control step size (256 steps) 0.39 % per step maximum volume attenuation ?48 db mute attenuation db adc outputs all zero codes group delay f s = 48 khz 910 s f s = 96 khz 460 s adc low-pass digital decimation filter characteristics 1 pass-band frequency 22 khz f s = 48 khz 44 khz f s = 96 khz stop-band frequency 26 khz f s = 48 khz 52 khz f s = 96 khz stop-band attenuation 120 db f s = 48 khz 120 db f s = 96 khz pass-band ripple 0.01 db f s = 48 khz 0.01 db f s = 96 khz adc high-pass digital filter characteristics cutoff frequency 0.9 hz f s = 48 khz src section resolution 24 bits sample rate 8 192 khz xin = 27 mhz src mclk 138 f s- max 33 mhz f s-max is the greater of the input or output sample rate maximum sample rate ratios upsampling 1:8 downsampling 7.75:1 dynamic range 140 20 hz to f s /2, 1 khz, ?60 dbfs input, f in = 44.1 khz, f out = 48 khz total harmonic distortion + noise 120 db 20 hz to f s /2, 1 khz, 0 dbfs input, f in = 44.1 khz, f out = 48 khz dac section number of channels 2 resolution 24 bits dynamic range 20 hz to 20 khz, ?60 db input unweighted 99 db f s = 48 khz 98 db f s = 96 khz a-weighted 97 101 db f s = 48 khz 100 db f s = 96 khz total harmonic distortion + noise referenced to 1v rms ?91 db f s = 48 khz ?90 db f s = 96 khz analog outputs output range ( full scale) 1.0 v rms output resistance 60 common-mode output voltage 1.5 v dc accuracy gain error ?2 ?0.8 db interchannel gain mismatch 0.05 db gain drift 1 mdb/c dc offset ?30 +30 mv
adav803 rev. a | page 5 of 60 parameter min typ max unit comments crosstalk (eiaj method) ?110 db phase deviation 0.05 degrees mute attenuation ?95.625 db volume control step size (256 steps) 0.375 db group delay 48 khz 630 s 96 khz 155 s 192 khz 66 s dac low-pass digital interpolation filter characteristics pass-band frequency 20 khz f s = 44.1 khz 22 khz f s = 48 khz 42 khz f s = 96 khz stop-band frequency 24 khz f s = 44.1 khz 26 khz f s = 48 khz 60 khz f s = 96 khz stop-band attenuation 70 db f s = 44.1 khz 70 db f s = 48 khz 70 db f s = 96 khz pass-band ripple 0.002 db f s = 44.1 khz 0.002 db f s = 48 khz 0.005 db f s = 96 khz pll section master clock input frequency 27/54 mhz generated system clocks mclko 27/54 mhz sysclk1 256 768 f s 256/384/512/768 32 khz/44.1 khz/48 khz sysclk2 256 768 f s 256/384/512/768 32 khz/44.1 khz/48 khz sysclk3 256 512 f s 256/512 32 khz/44.1 khz/48 khz jitter sysclk1 65 ps rms sysclk2 75 ps rms sysclk3 75 ps rms dir section input sample frequency 27.2 200 khz differential input voltage 200 mv dit section output sample frequency 27.2 200 khz digital i/o input voltage high, v ih 2.0 dvdd v input voltage low, v il 0.8 v input leakage, i ih @ v ih = 3.3 v 10 a input leakage, i il @ v il = 0 v 10 a output voltage high, v oh @ i oh = 0.4 ma 2.4 v output voltage low, v ol @ i ol = ?2 ma 0.4 v input capacitance 15 pf
adav803 rev. a | page 6 of 60 parameter min typ max unit comments power supplies voltage, avdd 3.0 3.3 3.6 v voltage, dvdd 3.0 3.3 3.6 v voltage, odvdd 3.0 3.3 3.6 v operating current all supplies at 3.3 v analog current 60 ma digital current 38 ma digital interface current 13 ma dirin/dirout current 5 ma pll current 18 ma power-down current reset low, no mclk analog current 18 ma digital current 2.5 ma digital interface current 700 a dirin/dirout current 3.5 ma pll current 900 a power supply rejection signal at analog supply pins ?70 db 1 khz, 300 mv p-p ?70 db 20 khz, 300 mv p-p 1 guaranteed by design.
adav803 rev. a | page 7 of 60 timing specifications timing specifications are guaranteed over the full temperature and supply range. table 3. parameter symbol min typ max unit comments master clock and reset mclki frequency f mclk 12.288 54 mhz xin frequency f xin 27 54 mhz reset low t reset 20 ns i 2 c port scl clock frequency f scl 400 khz scl high t sclh 0.6 s scl low t scll 1.3 s start condition setup time t scs 0.6 s relevant for repeated start condition hold time t sch 0.6 s after this period, the first clock is generated data setup time t ds 100 ns scl rise time t scr 300 ns scl fall time t scf 300 ns sda rise time t sdr 300 ns sda fall time t sdf 300 ns stop condition setup time t scs 0.6 s serial ports 1 slave mode xbclk high t sbh 40 ns xbclk low t sbl 40 ns xbclk frequency f sbf 64 f s xlrclk setup t sls 10 ns to xbclk rising edge xlrclk hold t slh 10 ns from xbclk rising edge xsdata setup t sds 10 ns to xbclk rising edge xsdata hold t sdh 10 ns from xbclk rising edge xsdata delay t sdd 10 ns from xbclk falling edge master mode xlrclk delay t mld 5 ns from xbclk falling edge xsdata delay t mdd 10 ns from xbclk falling edge xsdata setup t mds 10 ns from xbclk rising edge xsdata hold t mdh 10 ns from xbclk rising edge 1 the prefix x refers to i-, o-, iau x-, or oaux- for the full pin name. temperature range table 4. parameter min typ max unit specifications guaranteed 25 c functionality guaranteed ?40 +85 c storage ?65 +150 c
adav803 rev. a | page 8 of 60 absolute maximum ratings table 5. parameter rating dvdd to dgnd and odvdd to dgnd 0 v to 4.6 v avdd to agnd 0 v to 4.6 v digital inputs dgnd ? 0.3 v to dvdd + 0.3 v analog inputs agnd ? 0.3 v to avdd + 0.3 v agnd to dgnd ?0.3 v to +0.3 v reference voltage indefinite short circuit to ground soldering (10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adav803 rev. a | page 9 of 60 pin configuration and fu nction descriptions nc voutl nc voutr oauxsdata iauxlrclk iauxbclk iauxsdata z erol/int zeror dvdd dgnd advdd adgnd pll_lf2 pll_lf1 pll_gnd pll_vdd dgnd sysclk1 sysclk2 sysclk3 xin xout 39 38 37 41 40 mclko mclki dvdd dgnd 36 35 34 33 42 43 44 45 46 47 48 17 18 19 20 21 22 23 24 ilrclk ibclk isdata olrclk obclk osdata dirin odvdd odgnd ditout oauxlrclk oauxbclk 1 2 3 4 5 6 7 8 9 10 11 12 64 63 62 61 60 59 58 capln caplp agnd caprp caprn avdd agnd vref agnd filtd agnd avdd vinr vinl agnd avdd dir_lf dir_gnd dir_vdd reset ad0 sda scl ad1 13 14 15 16 25 26 27 31 3029 28 32 57 56 55 54 53 52 51 50 49 adav803 top view (not to scale) 04756-002 pin 1 indicator nc = no connect figure 2. adav803 pin configuration table 6. pin function descriptions pin no. mnemonic i/o description 1 vinr i analog audio input, right channel. 2 vinl i analog audio input, left channel. 3 agnd analog ground. 4 avdd analog voltage supply. 5 dir_lf dir phase-locked loop (pll) filter pin. 6 dir_gnd supply ground for dir analog sect ion. this pin should be connected to agnd. 7 dir_vdd supply for dir analog section. this pin should be connected to avdd. 8 reset i asynchronous reset input (active low). 9 ad0 i i 2 c address lsb. 10 sda i/o data input/output of i 2 c-compatible control interface. 11 scl i clock input of i 2 c compatible control interface. 12 ad1 i i 2 c address msb. 13 zerol/int o left channel (output) zero flag or interrupt (output) flag. the function of this pin is determined by the intrpt bit in dac control register 4. 14 zeror o right channel (output) zero flag. 15 dvdd digital voltage supply. 16 dgnd digital ground. 17 ilrclk i/o sampling clock (lrclk) of playback digital input port. 18 ibclk i/o serial clock (bclk) of playback digital input port. 19 isdata i data input of playback digital input port. 20 olrclk i/o sampling clock (lrclk) of record digital output port. 21 obclk i/o serial clock (bclk) of record digital output port. 22 osdata o data output of record digital output port. 23 dirin i input to digital input receiver (s/pdif). 24 odvdd interface digital voltage supply. 25 odgnd interface digital ground. 26 ditout o s/pdif output from dit.
adav803 rev. a | page 10 of 60 pin no. mnemonic i/o description 27 oauxlrclk i/o sampling clock (lrclk) of auxiliary digital output port. 28 oauxbclk i/o serial clock (bclk) of auxiliary digital output port. 29 oauxsdata o data output of auxiliary digital output port. 30 iauxlrclk i/o sampling clock (lrclk) of auxiliary digital input port. 31 iauxbclk i/o serial clock (bclk) of auxiliary digital input port. 32 iauxsdata i data input of auxiliary digital input port. 33 dgnd digital ground. 34 dvdd digital supply voltage. 35 mclki i external mclk input. 36 mclko o oscillator output. 37 xout i crystal input. 38 xin i crystal or external mclk input. 39 sysclk3 o system clock 3 (from pll2). 40 sysclk2 o system clock 2 (from pll2). 41 sysclk1 o system clock 1 (from pll1). 42 dgnd digital ground. 43 pll_vdd supply for pll analog section. this pin should be connected to avdd. 44 pll_gnd ground for pll analog section. this pin should be connected to agnd. 45 pll_lf1 loop filter for pll1. 46 pll_lf2 loop filter for pll2. 47 adgnd analog ground (mixed signal). this pin should be connected to agnd. 48 advdd analog voltage supply (mixed signal ). this pin should be connected to avdd. 49 voutr o right channel analog output. 50 nc no connect. 51 voutl o left channel analog output. 52 nc no connect. 53 avdd analog voltage supply. 54 agnd analog ground. 55 filtd output dac reference decoupling. 56 agnd analog ground. 57 vref voltage reference voltage. 58 agnd analog ground. 59 avdd analog voltage supply. 60 caprn adc modulator input filter capacitor (right channel, negative). 61 caprp adc modulator input filter capacitor (right channel, positive). 62 agnd analog ground. 63 caplp adc modulator input filter capacitor (left channel, positive). 64 capln adc modulator input filter capacitor (left channel, negative).
adav803 rev. a | page 11 of 60 typical performance characteristics frequency (normalized to f s ) magnitude (db) 0 ?50 ?100 ?150 0 0.5 1.0 1.5 2.0 04756-003 figure 3. adc composite filter response frequency (hz) magnitude (db) 5 ?5 0 ?15 ?10 ?25 ?20 ?30 0 5 10 15 20 04756-004 figure 4. adc high-pass filter response, f s = 48 khz frequency (hz) magnitude (db) 5 ?5 0 ?15 ?10 ?25 ?20 ?30 0 5 10 15 20 04756-005 figure 5. adc high-pass filter response, f s = 96 khz frequency (khz) magnitude (db) 0 ?50 ?100 ?150 0 96 192 288 384 04756-006 figure 6. dac composite filter response, 48 khz frequency (khz) magnitude (db) 0 ?50 ?100 ?150 02 4 12 36 48 04756-007 figure 7. dac pass-band filter response, 48 khz frequency (khz) magnitude (db) 0.06 0.04 0.02 0 ?0.06 ?0.04 ?0.02 081 6 04756-008 2 4 figure 8. dac filter ripple, 48 khz
adav803 rev. a | page 12 of 60 frequency (khz) magnitude (db) 0 ?50 ?100 ?150 0 192 384 576 768 04756-009 figure 9. dac composite filter response, 96 khz frequency (khz) magnitude (db) 0 ?50 ?100 ?150 0 2 44 87 29 04756-010 6 figure 10. dac pass-band filter response, 96 khz frequency (khz) magnitude (db) 0.10 0.05 0 ?0.05 ?0.10 0 2 44 87 29 04756-011 6 figure 11. dac filter ripple, 96 khz frequency (khz) magnitude (db) 0 ?50 ?100 ?150 ?200 0 384 768 1152 1536 04756-012 figure 12. dac composite filter response, 192 khz frequency (khz) magnitude (db) 0 ?2 ?4 ?6 ?8 ?10 48 64 80 96 04756-013 figure 13. dac pass-band filter response, 192 khz frequency (khz) magnitude (db) 0.50 0.40 0.30 0.20 0.10 0 ?0.10 ?0.30 ?0.40 ?0.20 ?0.50 0 8 16 32 64 04756-014 figure 14. dac filter ripple, 192 khz
adav803 rev. a | page 13 of 60 frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ?100 ?60 ?120 ?140 ?160 0 2 4 6 8 1012141618 20 04756-015 dnr = 102db (a-weighted) figure 15. dac dynamic range, f s = 48 khz frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ?100 ?60 ?120 ?140 ?160 02468101214161820 04756-016 thd+n = 96db figure 16. dac thd + n, f s = 48 khz frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ?100 ?60 ?120 ?140 ?160 0 5 10 15 20 25 30 35 40 45 48 04756-017 dnr = 102db (a-weighted) figure 17. dac dynamic range, f s = 96 khz frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ?100 ?60 ?120 ?140 ?160 0 5 10 15 20 25 30 35 40 45 48 04756-018 thd+n = 95db figure 18. dac thd + n, f s = 96 khz frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ?100 ?60 ?120 ?140 ?160 0 5 10 15 20 04756-019 dnr = 102db (a-weighted) figure 19. adc dynamic range, f s = 48 khz frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ?100 ?60 ?120 ?140 ?160 0 5 10 15 20 04756-020 thd+n = 92db (v in = ?3db) figure 20. dac thd + n, f s = 48 khz
adav803 rev. a | page 14 of 60 frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ?100 ?60 ?120 ?140 ?160 0 8 16 24 32 40 48 04756-021 dnr = 102db (a-weighted) frequency (khz) magnitude (db) 0 ?20 ?40 ?80 ?100 ?60 ?120 ?140 ?160 0 8 16 24 32 40 48 04756-022 thd+n = 92db (v in = ?3db) figure 21. adc dynamic range, f s = 96 khz figure 22. adc thd + n, f s = 96 khz
adav803 rev. a | page 15 of 60 functional description adc section the adav803s adc section is implemented using a second- order multibit (5 bits) - modulator. the modulator is sampled at either half of the adc mclk rate (modulator clock = 128 f s ) or one-quarter of the adc mclk rate (modulator clock = 64 f s ). the digital decimator consists of a sinc^5 filter followed by a cascade of three half-band fir filters. the sinc decimates by a factor of 16 at 48 khz and by a factor of 8 at 96 khz. each of the half-band filters decimates by a factor of 2. figure 23 shows the details of the adc section. by default, the adc assumes that the mclk rate is 256 times the sample rate. the adc can be clocked by a number of different clock sources to control the sample rate. mclk selection for the adc is set by internal clocking control register 1 (address 0x76). the adc provides an output word of up to 24 bits of resolution in twos complement format. the output word can be routed to the output ports, the sample rate converter, or the s/pdif digital transmitter. pll2 internal pll1 internal mclki xin reg 0x76 bits[4:2] reg 0x6f bits[1:0] dir pll(256 f s ) 04756-023 dir pll(512 f s ) adc mclk divider adc mclk adc figure 23. clock path control on the adc programmable gain amplifier (pga) the input of the record channel features a pga that converts the single-ended signal to a differential signal, which is applied to the analog - modulator of the adc. the pga can be programmed to amplify a signal by up to 24 db in 0.5 db increments. figure 24 shows the structure of the pga circuit. 4k ? to 64k ? 125 ? to modulator capxn capxp external capacitor (1nf npo) external capacitor (1nf npo) external capacitor (1nf npo) 8k ? 8k ? vref 04756-024 4k ? 125 ? figure 24. pga block diagram analog - modulator the adc features a second-order, multibit, - modulator. the input features two integrators in cascade followed by a flash converter. this multibit output is directed to a scrambler, followed by a dac for loop feedback. the flash adc output is also converted from thermometer coding to binary coding for input as a 5-bit word to the decimator. figure 25 shows the adc block diagram. the adc also features independent digital volume control for the left and right channels. the volume control consists of 256 linear steps, with each step reducing the digital output codes by 0.39%. each channel also has a peak detector that records the peak level of the input signal. the peak detector register is cleared by reading it. 04756-025 adc mclk amc (reg 0x6e bit 7) multibit - modulator decimator hpf peak detect volume control sinc^5 half-band filter modulator clock (6.144mhz max) 384khz 768khz sinc compensation 192khz 384khz half-band filter 96khz 192khz 48khz 96khz 2 4 figure 25. adc block diagram
adav803 rev. a | page 16 of 60 automatic level control (alc) the adc record channel features a programmable automatic level control block. this block monitors the level of the adc output signal and automatically reduces the gain, if the signal at the input pins causes the adc output to exceed a preset limit. this function can be useful to maximize the signal dynamic range when the input level is not well defined. the pga can be used to amplify the unknown signal, and the alc reduces the gain until the adc output is within the preset limits. this results in maximum front end gain. because the alc block monitors the output of the adc, the volume control function should not be used. the adc volume control scales the results from the adc, and any distortion caused by the input signal exceeding the input range of the adc is still present at the output of the adc, but scaled by a value determined by the volume control register. the alc block has two functions, attack mode and recovery mode. recovery mode consists of three settings: no recovery, normal recovery, and limited recovery. these modes are discussed in the following sections. figure 26 is a flow diagram of the alc block. when the alc has been enabled, any changes made to the pga or alc settings are ignored. to change the functionality of the alc, it must first be disabled. the settings can then be changed and the alc re-enabled. attack mode when the absolute value of the adc output exceeds the level set by the attack threshold bits in alc control register 2, attack mode is initiated. the pga gain for both channels is reduced by one step (0.5 db). the alc then waits for a time determined by the attack timer bits before sampling the adc output value again. if the adc output is still above the threshold, the pga gain is reduced by a further step. this procedure continues until the adc output is below the limit set by the attack threshold bits. the initial gains of the pgas are defined by the adc left pga gain register and the adc right pga gain register, and they can have different values. the alc subtracts a common gain offset to these values. the alc preserves any gain difference in db as defined by these registers. at no time do the pga gains exceed their initial values. the initial gain setting, therefore, also serves as a maximum value. the limit detection mode bit in alc control register 1 determines how the alc responds to an adc output that exceeds the set limits. if this bit is a 1, both channels must exceed the threshold before the gain is reduced. this mode can be used to prevent unnecessary gain reduction due to spurious noise on a single channel. if the limit detection mode bit is a 0, the gain is reduced when either channel exceeds the threshold. no recovery mode by default, there is no gain recovery. once the gain has been reduced, it is not recovered until the alc is reset, either by toggling the alcen bit in alc control register 1 or by writing any value to alc control register 3. the latter option is more efficient because it requires only one write operation to reset the alc function. no recovery mode prevents volume modulation of the signal caused by adjusting the gain, which can create undesirable artifacts in the signal. the gain can be reduced but not recovered. therefore, care should be taken that spurious signals do not interfere with the input signal because these might trigger a gain reduction unnecessarily. normal recovery mode normal recovery mode allows for the pga gain to be recovered, provided that the input signal meets certain criteria. first, the alc must not be in attack mode, that is, the pga gain has been reduced sufficiently such that the input signal is below the level set by the attack threshold bits. second, the output result from the adc must be below the level set by the recovery threshold bits in the alc control register. if both of these criteria are met, the gain is recovered by one step (0.5 db). the gain is incrementally restored to its original value, assuming that the adc output level is below the recovery threshold at intervals determined by the recovery time bits. if the adc output level exceeds the recovery threshold while the pga gain is being restored, the pga gain value is held and does not continue restoration until the adc output level is again below the recovery threshold. once the pga gain is restored to its original value, it is not changed again unless the adc output value exceeds the attack threshold and the alc then enters attack mode. care should be taken when using this mode to choose values for the attack and recovery thresholds that prevent excessive volume modulation caused by continuous gain adjustments. limited recovery mode limited recovery mode offers a compromise between no recov- ery and normal recovery modes. if the output level of the adc exceeds the attack threshold, attack mode is initiated. when attack mode has reduced the pga gain to suitable levels, the alc attempts to recover the gain to its original level. if the adc output level exceeds the level set by the recovery threshold bits, a counter is incremented (gaincntr). this counter is incremented at intervals equal to the recovery time selection, if the adc has any excursion above the recovery threshold. if the counter reaches its maximum value, determined by the gaincntr bits in alc control register 1, the pga gain is deemed suitable and no further gain recovery is attempted. whenever the adc output level exceeds the attack threshold, attack mode is reinitiated and the counter is reset.
adav803 rev. a | page 17 of 60 selecting a sample rate the output sample rate of the adc is always adc mclk/256, as shown in figure 23 . by default, the adc modulator runs at adc mclk/2. when the adc mclk exceeds 12.288 mhz, the adc modulator should be set to run at adc mclk/4. this is achieved by setting the amc (adc modulator clock) bit in the adc control register 1. to compensate for the reduced modulator clock speed, a different set of filters is used in the decimator section, ensuring that the sample rate remains the same. the amc bit can also be used to boost the thd + n perform- ance of the adc at the expense of dynamic range. the improvement is typically 0.5 db to 1.0 db and works because selecting the lower modulator rate reduces the amount of digital noise, improving thd + n, but also reduces the oversampling ratio, therefore reducing the dynamic range by a corresponding amount. for best performance of the adc, avoid using similar frequency clocks from separate sources in the adav803. for example, running the adc from a 12.288 mhz clock connected to mclki and using the pll to generate a separate 12.288 mhz clock for the dac can reduce the performance of the adc. this is due to the interaction of the clocks, which generate beat frequencies that can affect the charge on the switch capacitors of the analog inputs. wait for sample wait for sample wait for sample decrease gain by 0.5db and wait attack time is a recovery mode enabled? is sample greater than attack threshold? is sample above attack threshold? are all samples below recovery threshold? has gain been fully restored? yes yes yes no yes yes no no normal recovery increase gain by 0.5db wait recovery time limited recovery a tt a ck mode 04756-026 is sample above attack threshold? are all samples below recovery threshold? has gain been fully restored? is gaincntr at maximum? yes no no yes yes yes no no increase gain by 0.5db no increment gaincntr no no no has recovery time been reached? has recovery time been reached? figure 26. alc flow diagram
adav803 rev. a | page 18 of 60 dac section the adav803 has two dac channels arranged as a stereo pair with single-ended analog outputs. each channel has its own independently programmable attenuator, adjustable in 128 steps of 0.375 db per step. the dac can receive data from the playback or auxiliary input ports, the src, the adc, or the dir. each analog output pin sits at a dc level of vref, and swings 1.0 v rms for a 0 db digital input signal. a single op amp third-order external low-pass filter is recommended to remove high frequency noise present on the output pins. note that the use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band. care should be taken in selecting these components. the filtd and vref pins should be bypassed by external capacitors to agnd. the filtd pin is used to reduce the noise of the internal dac bias circuitry, thereby reducing the dac output noise. the voltage at the vref pin can be used to bias external op amps used to filter the output signals. for applications in which the vref is required to drive external op amps, which might draw more than 50 a or have dynamic load changes, extra buffering should be used to preserve the quality of the adav803 reference. the digital input data source for the dac can be selected from a number of available sources by programming the appropriate bits in the datapath control register. figure 27 shows how the digital data source and the mclk source for the dac are selected. each dac has an independent volume register giving 256 steps of control, with each step giving approximately 0.375 db of attenuation. note that the dacs are muted by default to prevent unwanted pops, clicks, and other noises from appearing on the outputs while the adav803 is being configured. each dac also has a peak-level register that records the peak value of the digital audio data. reading the register clears the peak. selecting a sample rate correct operation of the dac is dependent upon the data rate provided to the dac, the master clock applied to the dac, and the selected interpolation rate. by default, the dac assumes that the mclk rate is 256 times the sample rate, which requires an 8 oversampling rate. this combination is suitable for sample rates of up to 48 khz. for a 96 khz data rate that has a 24.576 mhz mclk (256 f s ) associated with it, the dac mclk divider should be set to divide the mclk by 2. this prevents the dac engine from running too fast. to compensate for the reduced mclk rate, the interpolator should be selected to operate in 4 (dac mclk = 128 f s ). similar combinations can be selected for different sample rates. 04756-027 pll2 internal pll1 internal mclki xin reg 0x76 bits[7:5] reg 0x65 bits[3:2] reg 0x63 bits[5:3] dir pll(256 f s ) dir pll(512 f s ) dir playback auxiliary in adc mclk divider dac mclk dac dac input figure 27. clock and datapath control on the dac multi-bit - modulator interpolator dac dac to zero flag pins from dac data path multiplexer volume/mute control peak detector zero detect to control registers analog output 04756-028 figure 28. dac block diagram
adav803 rev. a | page 19 of 60 sample rate converter (src) functional overview during asynchronous sample rate conversion, data can be converted at the same sample rate or at different sample rates. the simplest approach to an asynchronous sample rate conversion is to use a zero-order hold between the two samplers, as shown in figure 29 . in an asynchronous system, t2 is never equal to t1, nor is the ratio between t2 and t1 rational. as a result, samples at f s_out are repeated or dropped, producing an error in the resampling process. the frequency domain shows the wide side lobes that result from this error when the sampling of f s_out is convolved with the attenuated images from the sin(x)/x nature of the zero-order hold. the images at f s_in (dc signal images) of the zero-order hold are infinitely attenuated. because the ratio of t2 to t1 is an irrational number, the error resulting from the resampling at f s_out can never be eliminated. the error can be significantly reduced, however, through interpolation of the input data at f s_in . therefore, the sample rate converter in the adav803 is conceptually interpolated by a factor of 2 20 . 04756-029 zero-order hold f s_in =1/t1 f s_out = 1/t2 out in original signal sampled at f s_in sin(x)/x of zero-order hold spectrum of zero-order hold output spectrum of f s_out sampling f s_out 2 f s_out frequency response of f s_out convolved with zero-order hold spectrum figure 29. zero-order hold used by f s_ out to resample data from f s_in conceptual high interpolation model interpolation of the input data by a factor of 2 20 involves placing (2 20 ? 1) samples between each f s_in sample. figure 30 shows both the time domain and the frequency domain of interpolation by a factor of 2 20 . conceptually, interpolation by 2 20 involves the steps of zero-stuffing (2 20 ? 1) number of samples between each f s_in sample and convolving this interpolated signal with a digital low-pass filter to suppress the images. in the time domain, it can be seen that f s_out selects the closest f s_in 2 20 sample from the zero-order hold, as opposed to the nearest f s_in sample in the case of no interpolation. this significantly reduces the resampling error. 04756-030 f s_in f s_out out in interpolate by n low-pass filter zero-order hold time domain of f s_in samples time domain output of the low-pass filter time domain of f s_out resampling time domain of the zero-order hold output figure 30. src time domain in the frequency domain shown in figure 31 , the interpolation expands the frequency axis of the zero-order hold. the images from the interpolation can be sufficiently attenuated by a good low-pass filter. the images from the zero-order hold are now pushed by a factor of 2 20 closer to the infinite attenuation point of the zero-order hold, which is f s_in 2 20 . the images at the zero-order hold are the determining factor for the fidelity of the output at f s_out . 04756-031 f s_in f s_in 2 20 f s_in 2 20 f s_in 2 20 f s_in f s_out out in interpolate by n low-pass filter zero-order hold frequency domain of samples at f s_in frequency domain of the interpolation frequency domain of f s_out resampling frequency domain after resampling sin(x)/x of zero-order hold figure 31. frequency domain of the interpolation and resampling
adav803 rev. a | page 20 of 60 the worst-case images can be computed from the zero-order hold frequency response: maximum image = sin( f / f s_interp )/( f / f s_interp ) where: f is the frequency of the worst-case image that would be 2 20 f s_in f s_in /2. f s_interp = f s_in 2 20 . the following worst-case images would appear for f s_in equal to 192 khz: image at f s_interp ? 96 khz = ?125.1 db image at f s_interp + 96 khz = ?125.1 db hardware model the output rate of the low-pass filter in figure 30 is the interpolation rate: 2 20 192,000 khz = 201.3 ghz sampling at a rate of 201.3 ghz is clearly impractical, in addition to the number of taps required to calculate each interpolated sample. however, because interpolation by 2 20 involves zero-stuffing 2 20 ? 1 samples between each f s_in sample, most of the multiplies in the low-pass fir filter are by zero. a further reduction can be realized because only one interpolated sample is taken at the output at the f s_out rate, so only one convolution needs to be performed per f s_out period instead of 2 20 convolutions. a 64-tap fir filter for each f s_out sample is sufficient to suppress the images caused by the interpolation. one difficulty with the preceding approach is that the correct interpolated sample must be selected upon the arrival of f s_out . because there are 2 20 possible convolutions per f s_out period, the arrival of the f s_out clock must be measured with an accuracy of 1/201.3 ghz = 4.96 ps. measuring the f s_out period with a clock of 201.3 ghz frequency is clearly impossible; instead, several coarse measurements of the f s_out clock period are made and averaged over time. another difficulty with the preceding approach is the number of coefficients required. because there are 2 20 possible convolu- tions with a 64-tap fir filter, there must be 2 20 polyphase coefficients for each tap, which requires a total of 2 26 coeffi- cients. to reduce the number of coefficients in rom, the src stores a small subset of coefficients and performs a high order interpolation between the stored coefficients. the preceding approach works when f s_out > f s_in . however, when the output sample rate, f s_out , is less than the input sample rate, f s_in , the rom starting address, input data, and length of the convolution must be scaled. as the input sample rate rises over the output sample rate, the antialiasing filters cutoff frequency must be lowered because the nyquist frequency of the output samples is less than the nyquist frequency of the input samples. to move the cutoff frequency of the antialiasing filter, the coefficients are dynamically altered and the length of the convolution is increased by a factor of (f s_in /f s_out ). this technique is supported by the fourier transform property that, if f(t) is f(), then f(k t) is f(/k). thus, the range of decimation is limited by the size of the ram. src architecture the architecture of the sample rate converter is shown in figure 32 . the sample rate converters fifo block adjusts the left and right input samples and stores them for the fir filters convolution cycle. the f s_in counter provides the write address to the fifo block and the ramp input to the digital servo loop. the rom stores the coefficients for the fir filter convolution and performs a high order interpolation between the stored coefficients. the sample rate ratio block measures the sample rate for dynamically altering the rom coefficients and scaling of the fir filter length as well as the input data. the digital servo loop automatically tracks the f s_in and f s_out sample rates and provides the ram and rom start addresses for the start of the fir filter convolution. 04756-032 right data in left data in fifo digital servo loop f s_in counter rom a rom b rom c rom d f s_in f s_out sample rate ratio sample rate ratio external ratio high order interp fir filter l/r data out figure 32. architecture of the sample rate converter the fifo receives the left and right input data and adjusts the amplitude of the data for both the soft muting of the sample rate converter and the scaling of the input data by the sample rate ratio before storing the samples in the ram. the input data is scaled by the sample rate ratio because, as the fir filter length of the convolution increases, so does the amplitude of the convolution output. to keep the output of the fir filter from saturating, the input data is scaled down by multiplying it by (f s_out /f s_in ) when f s_out < f s_in . the fifo also scales the input data for muting and unmuting of the src. the ram in the fifo is 512 words deep for both left and right channels. an offset to the write address provided by the f s_in counter is added to prevent the ram read pointer from overlapping the write address. the minimum offset on the src is 16 samples. however, the group delay and mute-in register can be used to increase this offset. the number of input samples added to the write pointer of the fifo on the src is 16 plus bit 6 to bit 0 of the group delay register. this feature is useful in varispeed applications to prevent the read pointer to the fifo from running ahead of the write pointer. when set, bit 7 of the group delay and mute-in register soft-mutes the sample rate. increasing the offset of the
adav803 rev. a | page 21 of 60 write address pointer is useful for applications in which small changes in the sample rate ratio between f s_in and f s_out are expected. the maximum decimation rate can be calculated from the ram word depth and the group delay as (512 ? 16)/64 taps = 7.75 for short group delay and (512 ? 64)/64 taps = 7 for long group delay. the digital servo loop is essentially a ramp filter that provides the initial pointer to the address in ram and rom for the start of the fir convolution. the ram pointer is the integer output of the ramp filter, and the rom is the fractional part. the digital servo loop must provide excellent rejection of jitter on the f s_in and f s_out clocks, as well as measure the arrival of the f s_out clock within 4.97 ps. the digital servo loop also divides the fractional part of the ramp output by the ratio of f s_in /f s_out to dynamically alter the rom coefficients when f s_in > f s_out . 04756-033 dir pll(256 f s ) iclk2 iclk1 reg 0x00 bits[1:0] reg 0x77 bit[4:3] reg 0x76 bit[1:0] reg 0x62 bits[7:6] dir pll(512 f s ) dir playback auxiliary in adc mclki xin src mclk src output src src input pllint 2 pllint1 mclki xin pllint 2 pllint1 figure 33. clock and datapath control on the src the digital servo loop is implemented with a multirate filter. to settle the digital servo loop filter more quickly upon startup or a change in the sample rate, a fast mode has been added to the filter. when the digital servo loop starts up or the sample rate is changed, the digital servo loop enters fast mode to adjust and settle on the new sample rate. upon sensing that the digital servo loop is settling down to a reasonable value, the digital servo loop returns to normal (or slow) mode. during fast mode, the mute_ind bit in the s sample rate converter error register is asserted to let the user know that clicks or pops might be present in the digital audio data. the output of the src can be muted by asserting bit 7 of the group delay and mute register until the src has changed to slow mode. the mute_ind bit can be set to generate an interrupt when the src changes to slow mode, indicating that the data is being sample rate converted accurately. the frequency responses of the digital servo loop for fast mode and slow mode are shown in figure 34 . the fir filter is a 64-tap filter when f s_out f s_in and is (f s_in /f s_out ) 64 taps when f s_in > f s_out . the fir filter performs its convolution by loading in the starting address of the ram address pointer and the rom address pointer from the digital servo loop at the start of the f s_out period. the fir filter then steps through the ram by decrementing its address by 1 for each tap, and the rom pointer increments its address by the (f s_out /f s_in ) 2 20 ratio for f s_in > f s_out or 2 20 for f s_out f s_in . once the rom address rolls over, the convolution is completed. 04756-034 frequency (hz) magnitude (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 ?200 0.01 0.1 1 10 100 1k 10k 100k slow mode fast mode ?220 figure 34. frequency response of the digital servo loop; f s_in is the x-axis, f s_out = 192 khz, master clock is 30 mhz the convolution is performed for both the left and right channels, and the multiply accumulate circuit used for the convolution is shared between the channels. the f s_in /f s_out sample rate ratio circuit is used to dynamically alter the coefficients in the rom when f s_in > f s_out . the ratio is calculated by comparing the output of an f s_out counter to the output of an f s_in counter. if f s_out > f s_in , the ratio is held at one. if f s_in > f s_out , the sample rate ratio is updated, if it is different by more than two f s_out periods from the previous f s_out to f s_in comparison. this is done to provide some hysteresis to prevent the filter length from oscillating and causing distortion. figure 33 shows the detail of the src section. the src master clock is expected to be equal to 256 times the output sample rate. this master clock can be provided by four different clock sources. the selection is set by the src and clock control register (address 0x00), and the selected clock source can be divided using the same register.
adav803 rev. a | page 22 of 60 pll section the adav803 features a dual pll configuration to generate independent system clocks for asynchronous operation. figure 37 shows the block diagram of the pll section. the pll generates the internal and system clocks from a 27 mhz clock. this clock is generated either by a crystal connected between xin and xout, as shown in figure 35 , or from an external clock source connected directly to xin. a 54 mhz clock can also be used, if the internal clock divider is used. cc 04756-035 xtal xin xout figure 35. crystal connection both plls (pll1 and pll2) can be programmed independently and can accommodate a range of sampling rates (32 khz /44.1 khz/48 khz) with selectable system clock oversampling rates of 256 and 384. higher oversampling rates can also be selected by enabling the doubling of the sampling rate to give 512 or 768 f s ratios. note that this option also allows oversampling ratios of 256 or 384 at double sample rates of 64 khz /88.2 khz/96 khz. the pll outputs can be routed internally to act as clock sources for the other component blocks such as the adc and dac. the outputs of the plls are also available on the three sysclk pins. figure 38 shows how the plls can be configured to provide the sampling clocks. table 7. pll frequency selection options mclk selection pll sample rate, f s (khz) normal f s double f s 1 32/44.1/48 256/384 f s 512/768 f s 64/88.2/96 256/384 f s 2a 32/44.1/48 256/384 f s 512/768 f s 64/88.2/96 256/384 f s 2b same as f s selected for pll 2a 256/512 f s the plls require some external components to operate correctly. these components, shown in figure 36 , form a loop filter that integrates the current pulses from a charge pump and produces a voltage that is used to tune the vco. good quality capacitors, such as pps film, are recommended. figure 37 shows a block diagram of the pll section, including the master clock selection. figure 38 shows how the clock frequencies at the clock output pins, sysclk1 to sysclk3, and the internal pll clock values, pll1 and pll2, are selected. the clock nodes, pll1 and pll2, can be used as master clocks for the other blocks in the adav803, such as the dac or adc. the pll has separate supply and ground pins, which should be as clean as possible to prevent electrical noise from being converted into clock jitter by coupling onto the loop filter pins. 04756-036 pll block pll_lfx 732 ? 1.2f a v dd 10n f figure 36. pll loop filter 04756-037 mclki mclko xout xin reg 0x74 bit 5 reg 0x74 bit 4 reg 0x78 bit 6 reg 0x78 bit 7 phase detector and loop filter pll_lf1 pll1 sysclk1 sysclk2 sysclk3 pll_lf2 2 2 vco n output scaler n1 phase detector and loop filter pll2 vco n output scaler n2 output scaler n3 figure 37. pll sect ion block diagram
adav803 rev. a | page 23 of 60 04756-038 pll1 mclk pll2 mclk 48khz 32khz 44.1khz 256 384 reg 0x75 bits[3:2] reg 0x75 bit 0 reg 0x77 bit 0 reg 0x75 bit 1 pll1 pllint1 sysclk1 2 fs1 2 reg 0x75 bit 5 reg 0x75 bit 4 reg 0x77 bits[2:1] reg 0x75 bits[7:6] reg 0x74 bit 0 pll2 pllint2 sysclk2 sysclk3 48khz 32khz 44.1khz 256 384 2 fs2 fs3 2 2 256 512 figure 38. pll clocking scheme s/pdif transmitter and receiver the adav803 contains an integrated s/pdif transmitter and receiver. the transmitter consists of a single output pin, ditout, on which the biphase encoded data appears. the s/pdif transmitter source can be selected from the different blocks making up the adav803. additionally, the clock source for the s/pdif transmitter can be selected from the various clock sources available in the adav803. the receiver uses two pins, dirin and dir_lf. dirin accepts the s/pdif input data stream. the dirin pin can be configured to accept a digital input level, as defined in the specifications section, or an input signal with a peak-to-peak level of 200 mv minimum, as defined by the iec 60958-3 specification. dir_lf is a loop filter pin, required by the internal pll, which is used to recover the clock from the s/pdif data stream. the components shown in figure 42 form a loop filter, which integrates the current pulses from a charge pump and produces a voltage that is used to tune the vco of the clock recovery pll. the recovered audio data and audio clock can be routed to the different blocks of the adav803, as required. figure 39 shows a conceptual diagram of the dirin block. c* 04756-039 spdif *external capacitor is only required for variable level spdif inputs. comparator reg 0x7a bit 4 dirin dc level spdif receiver figure 39. dirin block 04756-040 dit input dit playback auxiliary in src reg 0x63 bits[2:0] adc dir ditout channel status and user bits figure 40. digital output transmitter block diagram 04756-041 dir dirin audio data recovered clock channel status/ user bits figure 41. digital input receiver block diagram 04756-042 dir block dir_lf 3.3k ? 100nf a v dd 6 .8n f figure 42. dir loop filter components
adav803 rev. a | page 24 of 60 serial digital audio transmission standards the adav803 can receive and transmit s/pdif, aes/ebu, and iec-958 serial streams. s/pdif is a consumer audio standard, and aes/ebu is a professional audio standard. iec-958 has both consumer and professional definitions. this data sheet is not intended to fully define or to provide a tutorial for these standards. contact the international standards-setting bodies for the full specifications. all these digital audio communication schemes encode audio data and audio control information using the biphase-mark method. this encoding method minimizes the dc content of the transmitted signal. as can be seen from figure 43 , 1s in the original data end up with midcell transitions in the biphase- mark encoded data, while 0s in the original data do not. note that the biphase-mark encoded data always has a transition between bit boundaries. 011100 04756-043 cloc k ( 2 times bit r ate) biphase-mark data data figure 43. biphase-mark encoding digital audio-communication schemes use preambles to distinguish among channels (called subframes) and among longer-term control information blocks (called frames). pream- bles are particular biphase-mark patterns, which contain encoding violations that allow the receiver to uniquely recognize them. these patterns and their relationship to frames and subframes are shown in table 8 and figure 44 . table 8. biphase-mark encode preamble biphase patterns channel x 11100010 or 00011101 left y 11100100 or 00011011 right z 11101000 or 00010111 left and cs block start xy zy xy 04756-044 preambles left ch frame 191 frame 0 frame 1 right ch left ch right ch left ch right ch subframe subframe figure 44. preambles, frames, and subframes the biphase-mark encoding violations are shown in figure 45 . note that all three preambles include encoding violations. ordinarily, the biphase-mark encoding method results in a polarity transition between bit boundaries. 11100010 11100100 11101000 04756-045 preamble x preamble y preamble z figure 45. preambles the serial digital audio communication scheme is organized using a frame and subframe construction. there are two subframes per frame (ordinarily the left and right channel). each subframe includes the appropriate 4-bit preamble, up to 24 bits of audio data, a validity (v) bit, a user (u) bit, a channel status (c) bit, and an even parity (p) bit. the channel status bits and the user bits accumulate over many frames to convey control information. the channel status bits accumulate over a 192 frame period (called a channel status block). the user bits accumulate over 1176 frames when the interconnect is imple- menting the so-called subcode scheme (eiaj cp-2401). the organization of the channel status block, frames, and subframes is shown in tabl e 9 and tabl e 10 . note that the adav803 supports the professional audio standard from a software point of view only. the digital interface supports only consumer mode. table 9. consumer audio standard data bits address 1 7 6 5 4 3 2 1 0 n channel status emphasis copy- right non- audio pro/ con = 0 n + 1 category code n + 2 channel number source number n + 3 reserved clock accuracy sampling frequency n + 4 reserved word length n + 5 to (n + 23) reserved 1 n = 0x20 for receiver channel status buffer. n = 0x38 for transmitter channel status buffer.
adav803 rev. a | page 25 of 60 table 10. professional audio standard data bits address 1 7 6 5 4 3 2 1 0 n sample frequency lock emphasis non- audio pro/con = 1 n + 1 user bit management channel mode n + 2 alignment level source word length use of auxiliary mode sample bits n + 3 channel identification n + 4 f s scaling sample frequency (f s ) reserved digital audio reference signal n + 5 reserved n + 6 alphanumeric channel origin datafirst character n + 7 alphanumeric channel origin data n + 8 alphanumeric channel origin data n + 9 alphanumeric channel origin datalast character n + 10 alphanumeric channel destination datafirst character n + 11 alphanumeric channel destination data n + 12 alphanumeric channel destination data n + 13 alphanumeric channel destination datalast character n + 14 local sample address codelsw n + 15 local sample address code n + 16 local sample address code n + 17 local sample address codemsw n + 18 time of day codelsw n + 19 time of day code n + 20 time of day code n + 21 time of day codemsw n + 22 reliability flags reserved n + 23 cyclic redundancy check character (crcc) 1 n = 0x20 for receiver channel status buffer. n = 0x38 for transmitter channel status buffer the standards allow the channel status bits in each subframe to be independent, but ordinarily the channel status bits in the two subframes of each frame are the same. the channel status bits are defined differently for the consumer audio standards and the professional audio standards. the 192 channel status bits are organized into 24 bytes and have the interpretations shown in table 9 and table 10 . the s/pdif transmitter and receiver have a comprehensive register set. the registers give the user full access to the functions of the s/pdif block, such as detecting nonaudio and validity bits, q subcodes, and preambles. the channel status bits as defined by the iec60958 and aes3 specifications are stored in register buffers for ease of use. an autobuffering function allows channel status bits and user bits read by the receiver to be copied directly to the transmitter block, removing the need for user intervention. receiver section the adav803 uses a double-buffering scheme to handle read- ing channel status and user bit information. the channel status bits are available as a memory buffer, taking up 24 consecutive register locations. the user bits are read using an indirect memory addressing scheme, where the receiver user bit indirect-address register is programmed with an offset to the user bit buffer, and the receiver user bit data register can be read to determine the user bits at that location. reading the receiver user bit data register automatically updates the indirect address register to the next location in the buffer. typically, the receiver user bit indirect-address register is programmed to zero (the start of the buffer), and the receiver user bit data register is read repeatedly until all the buffers data has been read. figure 46 and figure 47 show how receiving the channel status bits and user bits is implemented. 04756-046 second buffer receive cs buffer (0x20 to 0x37) channel status a (24 8 bits) channel status b (24 8 bits) rxcsswitch dirin s/pdif receive buffer first buffer figure 46. channel status buffer 04756-047 s/pdif 0.....7 8.....15 16.....23 first buffer 0.....7 8.....15 16.....23 user-bit buffer address = 0x50 address = 0x51 receiver user bit indirect address register receiver user bit data register figure 47. receiver user bit buffer the s/pdif receive buffer is updated continuously by the incoming s/pdif stream. once all the channel status bits for the block (192 for channel a and 192 for channel b) are received, the bits are copied into the receiver channel status buffer. this buffer stores all 384 bits of channel status information, and the rxcsswitch bit in the channel status switch buffer register determines whether the channel a or the channel b status bits are required to be read. the receive channel status bit buffer is 24 bytes long and spans the address range from 0x20 to 0x37. because the channel status bits of an s/pdif stream rarely change, a software interrupt/flag bit, rxcsbint, is provided to notify the host control either that a new block of channel status bits is available or that the first five bytes of channel status information have changed from a previous block. the function of the rxcsbint is controlled by the rxbconf3 bit in the receiver buffer configuration register.
adav803 rev. a | page 26 of 60 the size of the user bit buffer can be set by programming the rxbconf0 bit in the receiver buffer configuration register, as shown in table 11 . table 11. rxbconf3 functionality rxbconf0 receiver user bit buffer size 0 384 bits with preamble z as the start of the block. 1 768 bits with preamble z as the start of the block. the updating of the user bit buffer is controlled by bits rxbconf[2:1] and bit 7 to bit 4 of the channel status register, as shown in table 12 and table 13 . table 12. rxbconf[2:1] functionality rxbconf bit 2 bit 1 receiver user bit buffer configuration 0 0 user bits are ignored. 0 1 update second buffer when first buffer is full. 1 0 format according to byte 1, bit 4 to bit 7, if pro bit is set. format according to iec60958-3, if pro bit is clear. table 13. automatic user bit configuration bits 7 6 5 4 automatic receiver user bit buffer configuration 0 0 0 0 user bits are ignored. 0 1 0 0 aes-18 format: the user bit buffer is treated in the same way as when rxbconf[2:1] = 0b01. 1 0 0 0 user bit buffer is updated in the same way as when rxbconf[2:1] = 0b01 and rxbconf0 = 0b00. 1 1 0 0 user-defined format: the user bit buffer is treated in the same way as when rxbconf[2:1] = 0b01. when the user bit buffer has been filled, the rxubint interrupt bit in the interrupt status register is set, provided that the rxubint mask bit is set, to indicate that the buffer has new information and can be read. for the special case when the user data is formatted according to the iec 60958-3 standard into messages made of information units, called ius, the zeros stuffed between each iu and each message are removed and only the ius are stored. once the end of the message is sensed by more that eight zeros between ius, the user bit buffer is updated with the complete message and the first buffer begins looking for the start of the next message. each iu is stored as a byte consisting of 1, q, r, s, t, u, v, and w bits (see the iec 60958-3 specification for more information). when 96 ius are received, the q subcode of the ius is stored in the q subcode buffer, consisting of 10 bytes. the q subcode is the q bits taken from each of the 96 ius. the first 10 bytes (80 bits) of the q subcode contain information sent by cd, md, and dat systems. the last 16 bits of the q subcode are used to perform a crc check of the q subcode. if an error occurs in the crc check of the q subcode, the qcrcerror bit is set. this is a sticky bit that remains high until the register is read. transmitter operation the s/pdif transmitter has a similar buffer structure to the receive section. the transmitter channel status buffer occupies 24 bytes of the register map. this buffer is long enough to store the 192 bits required for one channel of channel status informa- tion. setting the txcsswitch bit determines if the data loaded to the transmitter channel status buffer is intended for channel a or channel b. in most cases, the channel status bits for channel a and channel b are the same, in which case setting the tx_a/b_same bit reads the data from the trans- mitter channel status buffer and transmits it on both channels. because the channel status information is rarely changed during transmission, the information contained in the buffer is transmitted repeatedly. the disable_tx_copy bit can be used to prevent the channel status bits from being copied from the transmitter cs buffer into the s/pdif transmitter buffer until the user has finished loading the buffers. this feature is typically used, if the channel a data and channel b data are different. setting the bit prevents the data from being copied. clearing the bit allows the data to be copied and then transmitted. figure 48 shows how the buffers are organized. 04756-048 txcsswitch transmit cs buffer (0x38 to 0x4f) channel status a (24 8 bits) channel status b (24 8 bits) ditout s/pdif transmit buffer figure 48. transmitter channel status buffer as with the receiver section, the transmitted user bits are also double-buffered. this is required because, unlike the channel status bits, the user bits do not necessarily repeat themselves. the user bits can be buffered in various configurations, as listed in table 14 . transmission of the user bits is determined by the state of the bconf3 bit. if the bit is 0, the user bits begin transmitting right away without alignment to the z preamble. if this bit is 1, the user bits do not start transmitting until a z preamble occurs when the txbconf[2:1] bits are 01. table 14. transmitter user bit buffer configurations txbconf2-1 bit 2 bit 1 transmitter user bit buffer configuration 0 0 zeros are transmitted for the user bits. 0 1 host writes user bits to the buffer until it is full. 1 0 writes the user bits to the buffer in ius specified by iec60958-3 and transmits them according to the standard. 1 1 first 10 bytes of the user-bit buffer are configured to store a q subcode.
adav803 rev. a | page 27 of 60 table 15. transmitter user bit buffer size txbconf0 buffer size 0 384 bits with preamble z as the start of the block. 1 768 bits with preamble z as the start of the block. by using sticky bits and interrupts, the transmit buffers can notify the host or microcontroller about their status. the sticky bit, txubint, is set when the transmit user bit buffer has been updated and the second transmit user bit buffer is empty and ready to accept new user bits. this bit is located in the interrupt status register. when the host reads the interrupt status register, this bit is cleared. interrupts for the txubint sticky bit can be enabled by setting the txubint mask bit in the interrupt status mask register 04756-049 s/pdif 0 0.....7 8.....15 16.....23 second buffer 0.....7 8.....15 16.....23 user-bit buffer address = 0x52 address = 0x53 transmitter user bit indirect address register transmitter user bit data register figure 49. transmitter user bit buffer autobuffering the adav803 s/pdif receiver and transmitter sections have an autobuffering mode allowing the channel status and user bits to be copied automatically from the receiver to the transmitter without user intervention. the channel status and user bits can be independently selected for autobuffering using the auto_csbits and auto_ubits bits, respectively, in the auto- buffer register. when the receiver and transmitter are running at the same sample rate, the transmitted channel status and user bits are the same as the received channel-status and user bits. in many systems, however, it is likely that the receiver and transmitter are not running at the same frequency. when the transmitter sample rate is higher than the receiver sample rate, the channel status and user bit blocks are sometimes repeated. when the transmitter sample rate is lower than the receiver sample rate, the channel status and user bit blocks might be dropped. because the first five bytes of the channel status are typically constant, they can be repeated or dropped with no information loss. however, if the pro bit in the channel status is set and the local sample address code and time-of-day code bytes contain information, these bytes might be repeated or dropped, in which case information can be lost. it is up to the user to determine how to handle this case. when the user bits are transmitted according to the iec 60958-3 format, the messages contained in the user bits can still be sent without dropping or repeating messages. because zero-stuffing is allowed between ius and messages, zeros can be added or subtracted to preserve the messages. when the transmitter sample rate is greater than the receiver sample rate, extra zeros are stuffed between the messages. when the sample rate of the transmitter is less than the sample rate of the receiver, the zeros stuffed between the messages are subtracted. if there are not enough zeros between the messages to be subtracted, the zeros between ius are subtracted as well. the zero_stuff_iu bit in the autobuffer register enables the adding or subtracting of zeros between messages. interrupts the adav803 provides interrupt bits to indicate the presence of certain conditions that require attention. reading the interrupt status register (register 0x1c) allows the user to determine if any of the interrupts have been asserted. the bits of the interrupt status register remain high, if set, until the register is read. two bits, srcerror and rxerror, indicate interrupt conditions in the sample rate converter and an s/pdif receiver error, respectively. both these conditions require a read of the appropriate error register (register 0x1a and register 0x18, respectively) to determine the exact cause of the interrupt. each interrupt in the interrupt status register has an associated mask bit in the interrupt status mask register. the interrupt mask bit must be set for the corresponding interrupt to be generated. this feature allows the user to determine which functions should be responded to. the dual function pin zerol/int can be set to indicate the presence of no audio data on the left channel or the presence of an interrupt set in the interrupt status register. as shown in table 16 , the function of this pin is selected by the intrpt bit in dac control register 4. table 16. zerol/int pin functionality intrpt pin functionality 0 pin functions as a zerol flag pin. 1 pin functions as an interrupt pin. serial data ports the adav803 contains four flexible serial ports (sports) to allow data transfer to and from the codec. all four sports are independent and can be configured as master or slave ports. in slave mode, the xlrclk and xbclk signals are inputs to the serial ports. in master mode, the serial port generates the xlrclk and xbclk signals. the master clock for the sport can be selected from a number of sources, as shown in figure 50 .
adav803 rev. a | page 28 of 60 04756-050 reg 0x76 bits[4:2] dir pll(512 f s ) dir pll(256 f s ) pllint1 pllint2 mclki xin iclk1 iclk2 pll clock reg 0x06 bits[5:4] mclk adc output port olrclk obclk osdata reg 0x76 bits[7:5] dir pll(512 f s ) dir pll(256 f s ) pllint1 pllint2 mclki xin iclk1 iclk2 pll clock reg 0x04 bits[4:3] mclk dac input port ilrclk ibclk isdata reg 0x77 bits[4:3] reg 0x00 bits[3:2] reg 0x00 bits[1:0] reg 0x00 bits[4:5] reg 0x76 bits[1:0] mclki xin pllint1 pllint2 iclk1 iclk2 dir pll(512 f s ) dir pll(256 f s ) reg 0x00 bits[7:6] mclki xin pllint1 pllint2 divider divider divider src mclk figure 50. sport clocking scheme care should be taken to ensure that the clock rate is appropriate for whatever block is connected to the serial port. for example, if the adc is running from the mclki input at 256 f s , then the master clock for the sport should also run from the mclki input to ensure that the adc and serial port are synchronized. the sports can be set to transmit or receive data in i 2 s, left- justified or right-justified formats with different word lengths by programming the appropriate bits in the playback register, auxiliary input port register, record register, and auxiliary output port-control register. figure 51 is a timing diagram of the serial data port formats. clocking scheme the adav803 provides a flexible choice of on-chip and off- chip clocking sources. the on-chip oscillator with dual plls is intended to offer complete system clocking requirements for use with available mpeg encoders, decoders, or a combination of codecs. the oscillator function is designed for generation of a 27 mhz video clock from a 27 mhz crystal connected between the xin and xout pins. capacitors must also be connected between these pins and dgnd, as shown in figure 35 . the capacitor values should be specified by the crystal manufacturer. a square wave version of the crystal clock is output on the mclko pin. if the system has a 27 mhz clock available, this clock can be connected directly to the xin pin. 04756-051 lrcl k bclk sdata lrcl k bclk sdata lrcl k bclk sdata lsb lsb lsb lsb lsb lsb left channel right channel right channel left channel left channel right channel msb msb msb msb msb msb right-justified mode ? select number of bits per channel i 2 s mode ? 16 bits to 24 bits per channel left-justified mode ? 16 bits to 24 bits per channel figure 51. seri al data modes
adav803 rev. a | page 29 of 60 datapath the adav803 features a digital input/output switching/ multiplexing matrix that gives flexibility to the range of possible input and output connections. digital input ports include playback and auxiliary input (both 3-wire digital), and s/pdif (single-wire to the on-chip receiver). output ports include the record and auxiliary output ports (both 3-wire digital) and the s/pdif port (single-wire from the on-chip transmitter). internally, the dir and dit are interfaced via 3-wire interfaces. the datapath for each input and output port is selected by programming datapath control register 1 and datapath control register 2. figure 52 shows the internal datapath structure of the adav803. 04756-052 pll adc dac oscillator reference control registers playback data input dir aux data input record data output aux data output dit src figure 52. datapath
adav803 rev. a | page 30 of 60 interface control the adav803 has a dedicated control port to allow the internal registers of the adav803 to be accessed. each of the internal registers is eight bits wide. where bits are described as reserved (res), these bits should be programmed as zero. i 2 c interface the i 2 c interface of the adav803 is a 2-wire interface consisting of a clock line, scl, and a data line, sda. sda is bidirectional; the adav803 drives sda to either acknowledge the master, ack, or send data during a read operation. the sda pin for the i 2 c port is an open-drain collector that requires a 1 k pull-up resistor. a write or read access occurs when the sda line is pulled low while the scl line is high, indicated by start in the timing diagrams. sda is allowed to change only when scl is low, except when a start or stop condition occurs, as shown in figure 53 and figure 54 . the i 2 c interface supports both standard (100 kbps) and fast (400 kbps) modes as defined by the i 2 c standards. the first eight bits of the access consist of the device address and the r/w bit. the device address consists of an internal built-in address (0b00100) and two address pins, ad1 and ad0. the two address pins allow up to four adav803s to be used in a system. initiating a write operation to the adav803 involves sending a start condition and then sending the device address with the r/w set low. the adav803 responds by issuing an ack to indicate that it has been addressed. the user then sends a second frame telling the adav803 which register is required to be written to. the 7-bit register address is left-shifted to make the eight bits that the frame requires. another ack is issued by the adav803. finally, the user can send another frame with the eight data bits required to be written to the register. a third ack is issued by the adav803, after which the user can send a stop condition to complete the data transfer. a read operation requires that the user first write to the adav803 to point to the correct register and then read the data. this is achieved by sending a start condition followed by the device address frame, with r/w low, and then the register address frame. following the ack from the adav803, the user must issue a repeated start condition. this is identical to a start condition. the next frame is the device address with r/w set high. on the next frame, the adav803 outputs the register data on the sda line. a stop condition completes the read operation. figure 53 and figure 54 show examples of writing to and read- ing from the dac left volume register (address 0b1101000). 0 0100 1 1 0 1 0 0 0 x 04756-053 sck sda ad1 ad0 r/w start by master ack. by adav803 ack. by adav803 ack. by adav803 stop by master frame 1 chip address byte sck (continued) sda (continued) frame 2 register address byte frame 3 data byte to adav803 d7 d6 d5 d4 d3 d2 d1 d0 figure 53. writing to the dac left volume register in i 2 c
adav803 rev. a | page 31 of 60 0 01 00ad1ad0 1 d7 ad1 ad0 d6 d5 d4 d3 d2 d1 d0 1 0 1 0 0 0 x 001 0 0 04756-054 scl sda start by master scl (continued) sda (continued) frame 1 chip address byte frame 3 chip address byte frame 4 register data frame 2 register address byte repeated start by master ack. by adav803 ack. by adav803 ack. by adav803 stop by master ack. by adav803 r/w r/w figure 54. reading from the dac left volume register in i 2 c block reads and writes the adav803 provides the user with the ability to write to or read from a block of registers in one continuous operation. to use this feature, the user has to continue providing data frames before the stop condition. for a write operation, the register address is automatically incremented with each additional frame and the register data is written to that register address. for a read operation, the register address is automatically incremented with each additional frame, and the register data is clocked out on that frame. care should be exercised when using the block read or block write modes. for most cases, block reading or writing to a register automatically increments the register address to point to the next register. the exceptions to this case are the indirect memory address registers, transmitter user bit and receiver user bit data buffers. using a block read or write to access these registers does not update the absolute register address, but instead updates the buffer address to provide the next value in the buffer.
adav803 rev. a | page 32 of 60 register descriptions src and clock controladdress 0000000 (0x00) table 17. src and clock control register bit map 7 6 5 4 3 2 1 0 srcdiv1 srcdiv0 clk2div1 clk2div0 clk1div1 clk1div0 mclksel1 mclksel0 table 18. src and clock control register bit descriptions bit name description srcdiv[1:0] divides the src master clock. 00 = src master clock is not divided. 01 = src master clock is divided by 1.5. 10 = src master clock is divided by 2. 11 = src master clock is divided by 3. clk2div[1:0] clock divider for internal clock 2 (iclk2). 00 = divide by 1. 01 = divide by 1.5. 10 = divide by 2. 11 = divide by 3. clk1div[1:0] clock divider for internal clock 1 (iclk1). 00 = divide by 1. 01 = divide by 1.5. 10 = divide by 2. 11 = divide by 3. mclksel[1:0] clock selection for the src master clock. 00 = internal clock 1. 01 = internal clock 2. 10 = pll recovered clock (512 f s ). 11 = pll recovered clock (256 f s ). s/pdif loopback cont roladdress 0000011 (0x03) table 19. s/pdif loopback control register bit map 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved reserved txmux table 20. s/pdif loopback cont rol register bit descriptions bit name description txmux selects the source for s/pdif output (ditout). 0 = s/pdif transmitter, normal mode. 1 = dirin, loopback mode.
adav803 rev. a | page 33 of 60 playback port controladdress 0000100 (0x04) table 21. playback port control register bit map 7 6 5 4 3 2 1 0 reserved reserved reserved clksrc1 clksrc0 spmode2 spmode1 spmode0 table 22. playback port control register bit descriptions bit name description clksrc[1:0] selects the clock source fo r generating the ilrclk and ibclk. 00 = input port is a slave. 01 = recovered pll clock. 10 = internal clock 1. 11 = internal clock 2. spmode[2:0] selects the serial format of the playback port. 000 = left-justified. 001 = i 2 s. 100 = 24-bit, right-justified. 101 = 20-bit, right-justified. 110 = 18-bit, right-justified. 111 = 16-bit, right-justified. auxiliary input portaddress 0000101 (0x05) table 23. auxiliary input port register bit map 7 6 5 4 3 2 1 0 reserved reserved reserved clksrc1 clksrc0 spmode2 spmode1 spmode0 table 24. auxiliary input port register bit descriptions bit name description clksrc[1:0] selects the clock source for generating the iauxlrclk and iauxbclk. 00 = input port is a slave. 01 = recovered pll cock. 10 = internal clock 1. 11 = internal clock 2. spmode[2:0] selects the serial format of auxiliary input port. 000 = left-justified. 001 = i 2 s. 100 = 24-bit, right-justified. 101 = 20-bit, right-justified. 110 = 18-bit, right-justified. 111 = 16-bit, right-justified.
adav803 rev. a | page 34 of 60 record port controladdress 0000110 (0x06) table 25. record port control register bit map 7 6 5 4 3 2 1 0 reserved reserved clksrc1 clksrc0 wlen1 wlen0 spmode1 spmode0 table 26. record port control register bit descriptions bit name description clksrc[1:0] selects the clock source for generating the olrclk and obclk. 00 = record port is a slave. 01 = recovered pll clock. 10 = internal clock 1. 11 = internal clock 2. wlen[1:0] selects the seri al output word length. 00 = 24 bits. 01 = 20 bits. 10 = 18 bits. 11 = 16 bits. spmode[1:0] selects the serial format of the record port. 00 = left-justified. 01 = i 2 s. 10 = reserved. 11 = right-justified. auxiliary output port address 0000111 (0x07) table 27. auxiliary output port register bit map 7 6 5 4 3 2 1 0 reserved reserved clksrc1 clksrc0 wlen1 wlen0 spmode1 spmode0 table 28. auxiliary output port register bit descriptions bit name description clksrc[1:0] selects the clock source for generating the oauxlrclk and oauxbclk. 00 = auxiliary record port is a slave. 01 = recovered pll clock. 10 = internal clock 1. 11 = internal clock 2. wlen[1:0] selects the seri al output word length. 00 = 24 bits. 01 = 20 bits. 10 = 18 bits. 11 = 16 bits. spmode[1:0] selects the serial format of the auxiliary record port. 00 = left-justified. 01 = i 2 s. 10 = reserved. 11 = right-justified.
adav803 rev. a | page 35 of 60 group delay and muteaddress 0001000 (0x08) table 29. group delay and mute register bit map 7 6 5 4 3 2 1 0 mute_src grpdly6 grpdly5 grpdly4 grpdly3 grpdly2 grpdly1 grpdly0 table 30. group delay and mute register bit descriptions bit name description mute_src soft-mutes the output of the sample rate converter. 0 = no mute. 1 = soft mute. grpdly[6:0] adds delay to the sample rate conv erter fir filter by grpdly[6:0] input samples. 0000000 = no delay. 0000001 = 1 sample delay. 0000010 = 2 sample delay. 1111110 = 126 sample delay. 1111111 = 127 sample delay. receiver configuratio n 1address 0001001 (0x09) table 31. receiver configuration 1 register bit map 7 6 5 4 3 2 1 0 noclock rxclk1 rxclk0 auto_deemph err1 err0 lock1 lock0 table 32. receiver configuration 1 register bit descriptions bit name description noclock selects the source of the rece iver clock when the pll is not locked. 0 = recovered pll clock is used. 1 = iclk1 is used. rxclk[1:0] determines the oversampling ratio of the recovered receiver clock. 00 = rxclk is a 128 f s recovered clock. 01 = rxclk is a 256 f s recovered clock. 10 = rxclk is a 512 f s recovered clock. 11 = reserved. auto_deemph automatically de-emphasizes the data from th e receiver based on the channel status information. 0 = automatic de-emphasis is disabled. 1 = automatic de-emphasis is enabled. err[1:0] defines what action the receiver should take, if the receiver detects a parity or biphase error. 00 = no action is taken. 01 = last valid sample is held. 10 = invalid sample is replaced with zeros. 11 = reserved. lock[1:0] defines what action the receiver should take, if the pll loses lock. 00 = no action is taken. 01 = last valid sample is held. 10 = zeros are sent out after the last valid sample. 11 = soft-mute of the last valid audio sample.
adav803 rev. a | page 36 of 60 receiver configuration 2address 0001010 (0x0a) table 33. receiver configuration 2 register bit map 7 6 5 4 3 2 1 0 rxmute sp_pll sp_pll_ sel1 sp_pll_ sel0 reserved reserved no nonaudio no_validity table 34. receiver configuration 2 register bit descriptions bit name description rxmute hard-mutes the audio output for the aes3/s/pdif receiver. 0 = aes3/s/pdif receiver is not muted. 1 = aes3/s/pdif receiver is muted. sp_pll aes3/s/pdif receiver pll accepts a left/right clock from one of the four serial ports as the pll reference clock. 0 = left/right clock generated from the aes3/s/pdif preambles is the reference clock to the pll. 1 = left/right clock from one of the serial ports is the reference clock to the pll. sp_pll_sel[1:0] selects one of the four serial ports as the reference clock to the pll when sp_pll is set. 00 = playback port is selected. 01 = auxiliary input port is selected. 10 = record port is selected. 11 = auxiliary output port is selected. no nonaudio when the no nonaudio bit is set, data from the aes3/s/pdif receiver is not allowed into the sample rate converter (src). if the no nonaudio data is due to dts, aac, an d so on, as defined by the iec61937 standard, then the data from the aes3/s/pdif receiver is not allowed into the src regardless of the state of this bit. 0 = aes3/s/pdif receiver data is sent to the src. 1 = data from the aes3/s/pdif receiver is not allo wed into the src, if the no nonaudio bit is set. no_validity when the no_validity bit is set, data from the aes3/s/pdif receiver is not allowed into the src. 0 = aes3/s/pdif receiver data is sent to the src. 1 = data from the aes3/s/pdif receiver is not allo wed into the src, if the no_validity bit is set.
adav803 rev. a | page 37 of 60 receiver buffer configur ationaddress 0001011 (0x0b) table 35. receiver buffer configuration register bit map 7 6 5 4 3 2 1 0 reserved reserved rxbconf5 rxbconf4 rxbconf3 rxbconf2 rxbconf1 rxbconf0 table 36. receiver buffer configuration register bit descriptions bit name description rxbconf5 if the user bits are formatted according to the iec60958-3 standard and the dat category is detected, the user bit interrupt is enabled only when there is a change in the start (id) bit. 0 = user bit interrupt is enabled in normal mode. 1 = if the dat category is detected, the user bit interrupt is enabled only if there is a change in the start (id) bit. rxbconf4 this bit determines whether channel a and channel b user bits are stored in the buffer together or separated between a and b. 0 = user bits are stored together. 1 = user bits are stored separately. rxbconf3 defines the function of rxcsbint. 0 = rxcsbint are set when a new block of receiver channel status is read, which is 192 audio frames. 1 = rxcsbint is set only if the first five bytes of the receiver channel status block changes from the previous channel status block. rxbconf[2:1] defines the user bit buffer. 00 = user bits are ignored. 01 = updates the second user bit buffer when the first user bit buffer is full. 10 = formats the received user bits according to byte 1, bit 4 to bit 7, of the channel status, if the pro bit is set. if the pro bit is not set, formats the user bits according to the iec60958-3 standard. 11 = reserved. rxbconf0 defines the user bit buffer size, if rxbconf[2:1] = 01. 0 = 384 bits with preamble z as the start of the buffer. 1 = 768 bits with preamble z as the start of the buffer. transmitter controladdress 0001100 (0x0c) table 37. transmitter control register bit map 7 6 5 4 3 2 1 0 reserved txvalidity txratio2 txratio1 txratio0 txclksel1 txclksel0 txenable table 38. transmitter control register bit descriptions bit name description txvalidity this bit is used to set or clear the validity bit in the aes3/s/pdif transmit stream. 0 = audio is suitable for digital-to-analog conversion. 1 = audio is not suitable for digital-to-analog conversion. txratio[2:0] determines the aes3/s/pdif tr ansmitter to aes3/s/pdif receiver ratio. 000 = transmitter to receiver ratio is 1:1. 001 = transmitter to receiver ratio is 1:2. 010 = transmitter to receiver ratio is 1:4. 101 = transmitter to receiver ratio is 2:1. 110 = transmitter to receiver ratio is 4:1. txclksel[1:0] selects the clock source for the aes3/s/pdif transmitter. 00 = internal clock 1 is the clock source for the transmitter. 01 = internal clock 2 is the clock source for the transmitter. 10 = recovered pll clock is the clock source for the transmitter. 11 = reserved. txenable enables the aes3/s/pdif transmitter. 0 = aes3/s/pdif transmitter is disabled. 1 = aes3/s/pdif transmitter is enabled.
adav803 rev. a | page 38 of 60 transmitter buffer config urationaddress 0001101 (0x0d) table 39. transmitter buffer configuration register bit map 7 6 5 4 3 2 1 0 iu_zeros3 iu_zeros2 iu_zeros1 iu_zeros0 txbconf3 txbconf2 txbconf1 txbconf0 table 40. transmitter buffer configuration register bit descriptions bit name description iu_zeros[3:0] determines the number of zeros to be s tuffed between ius in a message up to a maximum of 8. 0000 = 0. 0001 = 1. 0111 = 7. 1000 = 8. txbconf3 transmitter user bits can be stored in separate buffers or stored together. 0 = user bits are stored together. 1 = user bits are stored separately. txbconf[2:1] configures the transmitter user bit buffer. 00 = zeros are transmitted for the user bits. 01 = transmitter user bit buffer size is configured according to txbconf0. 10 = user bits are written to the transmit bu ffer in ius specified by the iec60958-3 standard. 11 = reserved. txbconf0 determines the buffer size of the tr ansmitter user bits when txbconf[2:1] is 01. 0 = 384 bits with preamble z as the start of the buffer. 1 = 768 bits with preamble z as the start of the buffer. channel status switch buffer and transmitteraddress 0001110 (0x0e) table 41. channel status switch buffe r and transmitter register bit map 7 6 5 4 3 2 1 0 reserved reserved tx_a/b_same disable_tx_copy reserved reserved txcsswitch rxcsswitch table 42. channel status switch buffer an d transmitter register bit description bit name description tx_a/b_same transmitter channel status a and b are the same. the trans mitter reads only from the channel status a buffer and places the data into the channel status b buffer. 0 = channel status for a and b are separate. 1 = channel status for a and b are the same. disable_tx_copy disables the copying of the channel status bits from the tr ansmitter channel status buffer to the s/pdif transmitter buffer. 0 = copying transmitter channel status is enabled. 1 = copying transmitter channel status is disabled. txcsswitch toggle switch for the transmit channel status buffer. 0 = 24-byte transmitter channel status a buffer can be accessed at address locations 0x38 through 0x4f. 1 = 24-byte transmitter channel status b buffer can be accessed at address locations 0x38 through 0x4f. rxcsswitch toggle switch for the receive channel status buffer. 0 = 24-byte receiver channel status a buffer can be accessed at address locations 0x20 through 0x37. 1 = 24-byte receiver channel status b buffer can be accessed at address locations 0x20 through 0x37.
adav803 rev. a | page 39 of 60 transmitter message zeros most si gnificant byteaddress 0001111 (0x0f) table 43. transmitter message zeros most significant byte register bit map 7 6 5 4 3 2 1 0 msbzeros7 msbzeros6 msbzeros5 msbzeros4 msbzeros3 msbzeros2 msbzeros1 msbzeros0 table 44. transmitter message zeros most si gnificant byte register bit description bit name description msbzeros[7:0] most significant byte of the number of zeros to be stuffed between iec60958-3 messages (packets). default = 0x00. transmitter message zeros least si gnificant byteaddress 0010000 (0x10) table 45. transmitter message zeros least significant byte register bit map 7 6 5 4 3 2 1 0 lsbzeros7 lsbzeros6 lsbzeros5 lsbzeros4 lsbzeros3 lsbzeros2 lsbzeros1 lsbzeros0 table 46. transmitter message zeros least si gnificant byte register bit descriptions bit name description lsbzeros[7:0] least significant byte of the number of zeros to be stuffed between iec60958-3 me ssages (packets). default = 0x09 . autobufferaddress 0010001 (0x11) table 47. autobuffer register bit map 7 6 5 4 3 2 1 0 reserved zero_stuff_iu auto_ubits auto_csbits iu_zeros3 iu_zeros2 iu_zeros1 iu_zeros0 table 48. autobuffer register bit descriptions bit name description zero_stuff_iu enables the addition or subtraction of zeros betw een ius during autobuffering of the user bits in iec60958-3 form at. 0 = no zeros added or subtracted. 1 = zeros can be added or subtracted between ius. auto_ubits enables the user bits to be autobuffered between the aes3/s/pdif receiver and transmitter. 0 = user bits are not autobuffered. 1 = user bits are autobuffered. auto_csbits enables the channel status bits to be autobu ffered between the aes3/s/pdif receiver and transmitter. 0 = channel status bits are not autobuffered. 1 = channel status bits are autobuffered. iu_zeros[3:0] sets the maximum number of zero-stuffing to be added between ius while autobuffering up to a maximum of 8. 0000 = 0. 0001 = 1. 0111 = 7. 1000 = 8. sample rate ratio ms baddress 0010010 (0x12) table 49. sample rate ratio ms b register (read-only) bit map 7 6 5 4 3 2 1 0 reserved srcratio14 srcratio13 srcratio12 srcratio11 srcratio10 srcratio09 srcratio08 table 50. sample rate ratio msb regi ster (read-only) bit descriptions bit name description srcratio[14:8] seven most significant bi ts of the15-bit sample rate ratio.
adav803 rev. a | page 40 of 60 sample rate ratio ls baddress 0010011 (0x13) table 51. sample rate ratio ls b register (read-only) bit map 7 6 5 4 3 2 1 0 srcratio07 srcratio06 srcratio05 srcratio04 srcratio03 srcratio02 srcratio01 srcratio00 table 52. sample rate ratio lsb regi ster (read-only) bit descriptions bit name description srcratio[7:0] eight least significant bits of the15-bit sample rate ratio. preamble-c msbaddress 0010100 (0x14) table 53. preamble-c msb register (read-only) bit map 7 6 5 4 3 2 1 0 pre_c15 pre_c14 pre_c13 pre_c12 pre_c11 pre_c10 pre_c9 pre_c8 table 54. preamble-c msb register (read-only) bit descriptions bit name description pre_c[15:8] eight most significant bits of the 16-bit preamble-c, when nonaudio data is detected according to the iec60937 standard; otherwise, bits show zeros. preamble-c lsbaddress 0010101 (0x15) table 55. preamble-c lsb register (read-only) bit map 7 6 5 4 3 2 1 0 pre_c07 pre_c06 pre_c05 pre_c04 pre_c03 pre_c02 pre_c01 pre_c00 table 56. preamble-c lsb register (read-only) bit descriptions bit name description pre_c[7:0] eight least significant bits of the 16-bit preamble-c, wh en nonaudio data is detected according to the iec60937 standard; otherwise, bits show zeros. preamble-d msbaddress 0010110 (0x16) table 57. preamble-d msb register (read-only) bit map 7 6 5 4 3 2 1 0 pre_d15 pre_d14 pre_d13 pre_d12 pre_d11 pre_d10 pre_d9 pre_d8 table 58. preamble-d msb register (read-only) bit descriptions bit name description pre_d[15:8] eight most significant bits of the 16-bit preamble-d, when nonaudio data is detected according to the iec60937 standard; otherwise, bits show zeros. when subframe nonaud io is used, this becomes the eight most significant bits of the 16-bit preamble-c of channel b. preamble-d lsbaddress 0010111 (0x17) table 59. preamble-d lsb register (read-only) bit map 7 6 5 4 3 2 1 0 pre_d07 pre_d06 pre_d05 pre_d04 pre_d03 pre_d02 pre_d01 pre_d00 table 60. preamble-d lsb register (read-only) bit descriptions bit name description pre_d[7:0] eight least significant bits of the 16-bit preamble-d, wh en nonaudio data is detect ed according to the iec60937 standard; otherwise, bits show zeros. when subframe nonaud io is used, this becomes the eight most significant bits of the 16-bit preamble-c of channel b.
adav803 rev. a | page 41 of 60 receiver erroraddress 0011000 (0x18) table 61. receiver error register (read-only) bit map 7 6 5 4 3 2 1 0 rxvalidity emphasis nonaudio nonaudio preamb le crcerror nostream biphase/parity lock table 62. receiver error register (read-only) bit descriptions bit name description rxvalidity this is the validity bit in the aes3 received stream. emphasis this bit is set if the audio data is pre-emphasized. once it has been read, it remains high and does not generate an interrupt unless it changes state. nonaudio this bit is set when channel status bit 1 (nonaudio) is set. once it has been read , it does not generate another interrupt unless the data becomes audio or the type of nonaudio data changes. nonaudio preamble this bit is set if the audio data is no naudio due to the detection of a preamble . the nonaudio preamble type register indicates what type of preamble was detected. once read, it remains in its state and does not generate an interrupt unless it changes state. crcerror this bit is the error flag for th e channel status crcerror check. this bit does not clear until the receiver error reg ister is read. nostream this bit is set if there is no aes3/s/pdif stream present at the aes3/s/pdif receiver. once re ad, it remains high and does not generate an interrupt unless it changes state. biphase/parity this bit is set if a biphase or parity error occu rred in the aes3/s/pdif stream. this bit is not cleared until t he register is read. lock this bit is set if the pll has locked or cleared when the pll loses lock. once read , it remains in its state and does not generate an interrupt unless it changes state. receiver error maskaddress 0011001 (0x19) table 63. receiver error mask register bit map 7 6 5 4 3 2 1 0 rxvalidity mask emphasis mask nonaudio mask nonaudio preamble mask crcerror mask nostream mask biphase/parity mask lock mask table 64. receiver error mask register bit descriptions bit name description rxvalidity mask masks the rxvalidity bit from generating an interrupt. 0 = rxvalidity bit does no t generate an interrupt. 1 = rxvalidity bit generates an interrupt. emphasis mask masks the emphasis bi t from generating an interrupt. 0 = emphasis bit does no t generate an interrupt. 1 = emphasis bit generates an interrupt. nonaudio mask masks the nonaudio bi t from generating an interrupt. 0 = nonaudio bit does no t generate an interrupt. 1 = nonaudio bit generates an interrupt. nonaudio preamble mask masks the nonaudio pr eamble bit from generating an interrupt. 0 = nonaudio preamble bit does not generate an interrupt. 1 = nonaudio preamble bit generates an interrupt. crcerror mask masks the crcerror bi t from generating an interrupt. 0 = crcerror bit does not generate an interrupt. 1 = crcerror bit generates an interrupt. nostream mask masks the nostream bi t from generating an interrupt. 0 = nostream bit does no t generate an interrupt. 1 = nostream bit generates an interrupt. biphase/parity mask masks the biphase/pari ty bit from generating an interrupt. 0 = biphase/parity bit does not generate an interrupt. 1 = biphase/parity bit generates an interrupt. lock mask masks the lock bit from generating an interrupt. 0 = lock bit does not generate an interrupt. 1 = lock bit generates an interrupt.
adav803 rev. a | page 42 of 60 sample rate converter erroraddress 0011010 (0x1a) table 65. sample rate converter e rror register (read-only) bit map 7 6 5 4 3 2 1 0 reserved reserved reserved reserved too_slow ovrl ovrr mute_ind table 66. sample rate converter error register (read-only) bit descriptions bit name description too_slow this bit is set when the clock to the src is too slow, th at is, there are not enough clock cycles to complete the internal convolution. ovrl this bit is set when the left output data of the sample rate converter has gone over the full-scale range and has been clipped. this bit is not cleared until the register is read. ovrr this bit is set when the right output da ta of the sample rate converter has gone over the full-scale range and has been clipped. this bit is not cl eared until the register is read. mute_ind mute indicated. this bit is set when the src is in fast mo de and clicks or pops can be heard in the src output data. the output of the src can be muted, if required, until the sr c is in slow mode. once read, this bit remains in its state and does not generate an interru pt until it has changed state. sample rate converter erro r maskaddress 0011011 (0x1b) table 67. sample rate converter error mask register bit map 7 6 5 4 3 2 1 0 reserved reserved reserved reserved rese rved ovrl mask ovrr mask mute_ind mask table 68. sample rate converter erro r mask register bit descriptions bit name description ovrl mask masks the ovrl from generating an interrupt. 0 = ovrl bit does not generate an interrupt. 1 = ovrl bit generates an interrupt. ovrr mask masks the ovrr from generating an interrupt. 0 = ovrr bit does not generate an interrupt. 1 = ovrr bit generates an interrupt. reserved. mute_ind mask masks the mute_ind from generating an interrupt. 0 = mute_ind bit does no t generate an interrupt. 1 = mute_ind bit generates an interrupt.
adav803 rev. a | page 43 of 60 interrupt statusaddress 0011100 (0x1c) table 69. interrupt status register bit map 7 6 5 4 3 2 1 0 srcerror txcstint txubint txcsbint rxcsdiff rxubint rxcsbint rxerror table 70. interrupt status register bit descriptions bit name description srcerror this bit is set if one of the sample rate converter interrupts is asserted, and the host should immediately read the sample rate converter error register. this bit remains high until the interrupt status register is read. txcstint this bit is set if a write to the transmitter channel status bu ffer was made while transmitter channel status bits were being copied from the transmitter cs buffer to the s/pdif transmit buffer. txubint this bit is set if the s/pdif trans mit buffer is empty. this bit remains high until the interrupt status register is re ad. txcsbint this bit is set if the transmitter channel status bit buffer has transmitted its bloc k of channel status. this bit remains high until the interrupt status register is read. rxcsdiff this bit is set if the receiver channel st atus a block is different from the receiver channel status b clock. this bit remains high until read, but does not generate an interrupt. rxubint this bit is set if the receiver user bit buffer has a new bloc k or message. this bit remains high until the interrupt status register is read. rxcsbint this bit is set if a new block of channel status is read when rxbconf3 = 0, or if the channel status has changed when rxbconf3 = 1. this bit remains high unti l the interrupt status register is read. rxerror this bit is set if one of the aes3/s/pdif receiver interrupts is asserted, and the host should immediately read the receiver error register. this bit remains high unti l the interrupt status register is read. interrupt status mask address 0011101 (0x1d) table 71. interrupt status mask register bit map 7 6 5 4 3 2 1 0 srcerror mask txcstint mask txubint mask txcsbint ma sk reserved rxubint mask rxcsbint mask rxerror mask table 72. interrupt status mask register bit descriptions bit name description srcerror mask masks the srcerror bi t from generating an interrupt. 0 = srcerror bit does not generate an interrupt. 1 = srcerror bit generates an interrupt. txcstint mask masks the txcstint bit from generating an interrupt. 0 = txcstint bit does not generate an interrupt. 1 = txcstint bit generates an interrupt. txubint mask masks the txubint bit from generating an interrupt. 0 = txubint bit does not generate an interrupt. 1 = txubint bit generates an interrupt. txcsbint mask masks the txcsbint bit from generating an interrupt. 0 = txcsbint bit does not generate an interrupt. 1 = txcsbint bit generates an interrupt. rxubint mask masks the rxubint bit from generating an interrupt. 0 = rxubint bit does not generate an interrupt. 1 = rxubint bit generates an interrupt. rxcsbint mask masks the rxcsbint bit from generating an interrupt. 0 = rxcsbint bit does not generate an interrupt. 1 = rxcsbint bit generates an interrupt. rxerror mask masks the rxerror bit from generating an interrupt. 0 = rxerror bit does not generate an interrupt. 1 = rxerror bit generates an interrupt.
adav803 rev. a | page 44 of 60 mute and de-emphasi saddress 0011110 (0x1e) table 73. mute and de-emphasis register bit map 7 6 5 4 3 2 1 0 reserved reserved txmute reserved reserved src_deem1 src_deem0 reserved table 74. mute and de-emphasis register bit descriptions bit name description txmute mutes the aes3/s/pdif transmitter. 0 = transmitter is not muted. 1 = transmitter is muted. src_deem[1:0] selects the de-emphasis filter for the input data to the sample rate converter. 00 = no de-emphasis. 01 = 32 khz de-emphasis. 10 = 44.1 khz de-emphasis. 11 = 48 khz de-emphasis. nonaudio preamble typeaddress 0011111 (0x1f) table 75. nonaudio preamble type register (read-only) bit map 7 6 5 4 3 2 1 0 reserved reserved reserved reserved dts-cd preamble nonaudio frame nonaudio subframe_a nonaudio subframe_b table 76. nonaudio preamble type re gister (read-only) bit descriptions bit name description dts-cd preamble this bit is set if the dts-cd preamble is detected. nonaudio frame this bit is set if the data received through the aes3/s/ pdif receiver is nonaudio data according to the iec61937 standard or nonaudio data according to smpte337m. nonaudio subframe_a this bit is set if the data received through channel a of the aes3/s/pdif receiver is subframe nonaudio data according to smpte337m. nonaudio subframe_b this bit is set if the data received through channel b of the aes3/s/pdif receiver is subframe nonaudio data according to smpte337m. receiver channel status bufferadd ress 0100000 to address 0110111 (0x20 to 0x37) table 77. receiver channel status buffer register bit map 7 6 5 4 3 2 1 0 rcsb7 rcsb6 rcsb5 rcsb4 rcsb3 rcsb2 rcsb1 rcsb0 table 78. receiver channel status buffer register bit descriptions bit name description rcsb[7:0] the 24-byte receiver channel status buffer. the pro bit is stor ed at address location 0x20, bit 0. this buffer is read- only if the channel status is not autobuffered between the receiver and transmitter. transmitter channel status bufferadd ress 0111000 to address 1001111 (0x38 to 0x4f) table 79. transmitter channel status buffer register bit map 7 6 5 4 3 2 1 0 tcsb7 tcsb6 tcsb5 tcsb4 tcsb3 tcsb2 tcsb1 tcsb0 table 80. transmitter channel status buffer register bit descriptions bit name description tcsb[7:0] the 24-byte transmitter channel status buffer. the pro bit is stored at address location 0x38, bit 0. this buffer is disabled when autobuffering between the receiver and transmitter is enabled.
adav803 rev. a | page 45 of 60 receiver user bit buffer indire ct address address 1010000 (0x50) table 81. receiver user bit buffer indirect address register bit map 7 6 5 4 3 2 1 0 rxubaddr7 rxubaddr6 rxubaddr5 rxubaddr4 rxubaddr3 rxub addr2 rxubaddr1 rxubaddr0 table 82. receiver user bit buffer indirect address register bit descriptions bit name description rxubaddr[7:0] indirect address pointing to the addr ess location in the receiver user bit buffer. receiver user bit buffer dataaddress 1010001 (0x51) table 83. receiver user bit buffer data register bit map 7 6 5 4 3 2 1 0 rxubdata7 rxubdata6 rxubdata5 rxubdata4 rxubdata3 rxubdata2 rxubdata1 rxubdata0 table 84. receiver user bit buffer data register bit descriptions bit name description rxubdata[7:0] a read from this register reads eight bits of user data from the receiver user bit buffer pointed to by rxubaddr0[7:0]. this buffer can be written to when aut obuffering of the user bits is enabled; otherwise, it is a read-only buffer. transmitter user bit buffer indirect addressaddress 1010010 (0x52) table 85. transmitter user bit buffer indirect address register bit map 7 6 5 4 3 2 1 0 txubaddr7 txubaddr6 txubaddr5 txubaddr4 txubaddr3 txubaddr2 txubaddr1 txubaddr0 table 86. transmitter user bit buffer indirect address register bit descriptions bit name description txubaddr[7:0] indirect address pointing to the addr ess location in the transmitter user bit buffer. transmitter user bit buff er dataaddress 1010011 (0x53) table 87. transmitter user bit buffer data register bit map 7 6 5 4 3 2 1 0 txubdata7 txubdata6 txubdata5 txubdata4 txubdata3 txubdata2 txubdata1 txubdata0 table 88. transmitter user bit buffer data register bit descriptions bit name description txubdata[7:0] a write to this register writes eight bi ts of user data to the transmit user bit buffer pointed to by txubaddr0[7:0]. when user bit autobuffering is en abled, this buffer is disabled. q subcode crcerror statusaddress 1010100 (0x54) table 89. q subcode crcerror stat us register (read-only) bit map 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved qcrcerror qsub table 90. q subcode crcerror status re gister (read-only) bit descriptions bit name description qcrcerror this bit is set if the crc check of the q subcode fails. this bit remains high, but does not generate an interrupt. this bit is cleared once the register is read. qsub this bit is set if a q subcode has been read into the q subcode buffer (see table 91 ).
adav803 rev. a | page 46 of 60 q subcode bufferaddress 0x55 to address 0x5e table 91. q subcode buffer bit map address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x55 address address address address control control control control 0x56 track number track number track number track number track number track number track number track number 0x57 index index index index index index index index 0x58 minute minute minute minute minute minute minute minute 0x59 second second second second second second second second 0x5a frame frame frame frame frame frame frame frame 0x5b zero zero zero zero zero zero zero zero 0x5c absolute minute absolute minute absolute minute absolute minute absolute minute absolute minute absolute minute absolute minute 0x5d absolute second absolute second absolute second absolute second absolute second absolute second absolute second absolute second 0x5e absolute frame absolute frame absolute frame absolute frame absolute frame absolute frame absolute frame absolute frame datapath control regist er 1address 1100010 (0x62) table 92. datapath control register 1 bit map 7 6 5 4 3 2 1 0 src1 src0 rec2 rec1 rec0 auxo2 auxo1 auxo0 table 93. datapath control register 1 bit descriptions bit name description src[1:0] datapath source select for sample rate converter (src). 00 = adc. 01 = dir. 10 = playback. 11 = auxiliary in. rec[2:0] datapath source select for record output port. 000 = adc. 001 = dir. 010 = playback. 011 = auxiliary in. 100 = src. auxo[2:0] datapath source select for auxiliary output port. 000 = adc. 001 = dir. 010 = playback. 011 = auxiliary in. 100 = src.
adav803 rev. a | page 47 of 60 datapath control regist er 2address 1100011 (0x63) table 94. datapath control register 2 bit map 7 6 5 4 3 2 1 0 reserved reserved dac2 dac1 dac0 dit2 dit1 dit0 table 95. datapath control register 2 bit descriptions bit name description dac[2:0] datapath source select for dac. 00 = adc. 01 = dir. 10 = playback. 11 = auxiliary in. 100 = src. dit[2:0] datapath source select for dit. 000 = adc. 001 = dir. 010 = playback. 011 = auxiliary in. 100 = src. dac control register 1address 1100100 (0x64) table 96. dac control register 1 bit map 7 6 5 4 3 2 1 0 dr_all dr_dig chsel1 chsel0 pol1 pol0 muter mutel table 97. dac control register 1 bit descriptions bit name description dr_all hard reset and power-down. 0 = normal, output pins go to v ref level. 1 = hard reset and low power, output pins go to agnd. dr_dig dac digital reset. 0 = normal. 1 = reset all except registers. chsel[1:0] dac channel select. 00 = normal, left-right. 01 = both right. 10 = both left. 11 = swapped, right-left. pol[1:0] dac channel polarity. 00 = both positive. 01 = left negative. 10 = right negative. 11 = both negative. muter mute right channel. 0 = mute. 1 = normal. mutel mute left channel. 0 = mute. 1 = normal.
adav803 rev. a | page 48 of 60 dac control register 2address 1100101 (0x65) table 98. dac control register 2 bit map 7 6 5 4 3 2 1 0 reserved reserved dmclk1 dmclk0 dfs1 dfs0 deem1 deem0 table 99. dac control register 2 bit descriptions bit name description dmclk[1:0] dac mclk divider. 00 = mclk. 01 = mclk/1.5. 10 = mclk/2. 11 = mclk/3. dfs[1:0] dac interpolator select. 00 = 8 (mclk = 256 f s ). 01 = 4 (mclk = 128 f s ). 10 = 2 (mclk = 64 f s ). 11 = reserved. deem[1:0] dac de-emphasis select. 00 = none. 01 = 44.1 khz. 10 = 32 khz. 11 = 48 khz. dac control register 3address 1100110 (0x66) table 100. dac control register 3 bit map 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved zfvol zfdata zfpol table 101. dac control register 3 bit descriptions bit name description zfvol dac zero flag on mute and zero volume. 0 = enabled. 1 = disabled. zfdata dac zero flag on zero data disable. 0 = enabled. 1 = disabled. zfpol dac zero flag polarity. 0 = active low. 1 = active high.
adav803 rev. a | page 49 of 60 dac control register 4address 1100111 (0x67) table 102. dac control register 4 bit map 7 6 5 4 3 2 1 0 reserved intrpt zerosel1 zerosel0 reserved reserved reserved reserved table 103. dac control register 4 bit descriptions bit name description intrpt this bit selects the functionality of the zerol/int pin. 0 = pin functions as a zerol flag pin. 1 = pin functions as an interrupt pin. zerosel[1:0] these bits control the functionality of the ze ror pin when the zerol/int pin is used as an interrupt. 00 = pin functions as a zeror flag pin. 01 = pin functions as a zerol flag pin. 10 = pin is asserted when either the left or right channel is zero. 11 = pin is asserted when both the left and right channels are zero. dac left volumeaddress 1101000 (0x68) table 104. dac left volume register bit map 7 6 5 4 3 2 1 0 dvoll7 dvoll6 dvoll5 dvoll4 dvoll3 dvoll2 dvoll1 dvoll0 table 105. dac left volume register bit descriptions bit name description dvoll[7:0] dac left channel volume control. 1111111 = 0 dbfs. 1111110 = ?0.375 dbfs. 0000000 = ?95.625 dbfs. dac right volumeaddress 1101001 (0x69) table 106. dac right volume register bit map 7 6 5 4 3 2 1 0 dvolr7 dvolr6 dvolr5 dvolr4 dvolr3 dvolr2 dvolr1 dvolr0 table 107. dac right volume register bit descriptions bit name description dvolr[7:0] dac right channel volume control. 1111111 = 0 dbfs. 1111110 = ?0.375 dbfs. 0000000 = ?95.625 dbfs. dac left peak volumeaddress 1101010 (0x6a) table 108. dac left peak volume register bit map 7 6 5 4 3 2 1 0 reserved reserved dlp5 dlp4 dlp3 dlp2 dlp1 dlp0 table 109. dac left peak volume register bit descriptions bit name description dlp[5:0] dac left channel peak volume detection. 000000 = 0 dbfs. 000001 = ?1 dbfs. 111111 = ?63 dbfs.
adav803 rev. a | page 50 of 60 dac right peak volumeaddress 1101011 (0x6b) table 110. dac right peak volume register bit map 7 6 5 4 3 2 1 0 reserved reserved drp5 drp4 drp3 drp2 drp1 drp0 table 111. dac right peak volume register bit descriptions bit name description drp[5:0] dac right channel peak volume detection. 000000 = 0 dbfs. 000001 = ?1 dbfs. 111111 = ?63 dbfs. adc left channel pga gainaddress 1101100 (0x6c) table 112. adc left channel pga gain register bit map 7 6 5 4 3 2 1 0 reserved reserved agl5 agl4 agl3 agl2 agl1 agl0 table 113. adc left channel pga gain register bit descriptions bit name description agl[5:0] pga left channel gain control. 000000 = 0 db. 000001 = 0.5 db. 101111 = 23.5 db. 110000 = 24 db. 111111 = 24 db. adc right channel pga gainaddress 1101101 (0x6d) table 114. adc right channel pga gain register bit map 7 6 5 4 3 2 1 0 reserved reserved agr5 agr4 agr3 agr2 agr1 agr0 table 115. adc right channel pga gain register bit descriptions bit name description agr[5:0] pga right channel gain control. 000000 = 0 db. 000001 = 0.5 db. 101111 = 23.5 db. 110000 = 24 db. 111111 = 24 db.
adav803 rev. a | page 51 of 60 adc control register 1address 1101110 (0x6e) table 116. adc control register 1 bit map 7 6 5 4 3 2 1 0 amc hpf pwrdwn ana_pd muter mutel plpd prpd table 117. adc control register 1 bit descriptions bit name description amc adc modulator clock. 0 = adc mclk/2 (128 f s ). 1 = adc mclk/4 (64 f s ). hpf high-pass filter enable. 0 = normal. 1 = hpf enabled. pwrdwn adc power-down. 0 = normal. 1 = power-down. ana_pd adc analog section power-down. 0 = normal. 1 = power-down. muter mute adc right channel. 0 = normal. 1 = muted. mutel mute adc left channel. 0 = normal. 1 = muted. plpd pga left power-down. 0 = normal. 1 = power-down. prpd pga right power-down. 0 = normal. 1 = power-down. adc control register 2address 1101111 (0x6f) table 118. adc control register 2 bit map 7 6 5 4 3 2 1 0 reserved reserved reserved buf_pd reserved reserved mcd1 mcd0 table 119. adc control register 2 bit descriptions bit name description buf_pd reference buffer power-down control. 0 = normal. 1 = power-down. mcd[1:0] adc master clock divider. 00 = divide by 1. 01 = divide by 2. 10 = divide by 3. 11 = divide by 1.
adav803 rev. a | page 52 of 60 adc left volumeaddress 1110000 (0x70) table 120. adc left volume register bit map 7 6 5 4 3 2 1 0 avoll7 avoll6 avoll5 avoll4 avoll3 avoll2 avoll1 avoll0 table 121. adc left volume register bit descriptions bit name description avoll[7:0] adc left channel volume control. 1111111 = 1.0 (0 dbfs). 1111110 = 0.996 (?0.00348 dbfs). 1000000 = 0.5 (?6 dbfs). 0111111 = 0.496 (?6.09 dbfs). 0000000 = 0.0039 (?48.18 dbfs). adc right volumeaddress 1110001 (0x71) table 122. adc right volume register bit map 7 6 5 4 3 2 1 0 avolr7 avolr6 avolr5 avolr4 avolr3 avolr2 avolr1 avolr0 table 123. adc right volume register bit descriptions bit name description avolr[7:0] adc right channel volume control. 1111111 = 1.0 (0 dbfs). 1111110 = 0.996 (?0.00348 dbfs). 1000000 = 0.5 (?6 dbfs). 0111111 = 0.496 (?6.09 dbfs). 0000000 = 0.0039 (?48.18 dbfs). adc left peak volume address 1110010 (0x72) table 124. adc left peak volume register bit map 7 6 5 4 3 2 1 0 reserved reserved alp5 alp4 alp3 alp2 alp1 alp0 table 125. adc left peak volume register bit descriptions bit name description alp[5:0] adc left channel peak volume detection. 000000 = 0 dbfs. 000001 = ?1 dbfs. 111111 = ?63 dbfs. adc right peak volumeaddress 1110011 (0x73) table 126. adc right peak volume register bit map 7 6 5 4 3 2 1 0 reserved reserved arp5 arp4 arp3 arp2 arp1 arp0 table 127. adc right peak volume register bit descriptions bit name description arp[5:0] adc right channel peak volume detection. 000000 = 0 dbfs. 000001 = ?1 dbfs. 111111 = ?63 dbfs.
adav803 rev. a | page 53 of 60 pll control register 1address 1110100 (0x74) table 128. pll control register 1 bit map 7 6 5 4 3 2 1 0 dirin_clk1 dirin_clk0 mclkodiv plldiv pll2pd pll1pd xtlpd sysclk3 table 129. pll control register 1 bit descriptions bit name description dirin_clk[1:0] recovered s/pdif clock sent to sysclk3. 00 = sysclk3 comes from pll block. 01 = reserved. 10 = reserved. 11 = sysclk3 is the recovered s/pdif clock from dirin. mclkodiv divide input mclk by 2 to generate mclko. 0 = disabled. 1 = enabled. plldiv divide xin by 2 to generate the pll master clock. 0 = disabled. 1 = enabled. pll2pd power-down pll2. 0 = normal. 1 = power-down. pll1pd power-down pll1. 0 = normal. 1 = power-down. xtlpd power-down xtal oscillator. 0 = normal. 1 = power-down. sysclk3 clock output for sysclk3. 0 = 512 f s . 1 = 256 f s .
adav803 rev. a | page 54 of 60 pll control register 2address 1110101 (0x75) table 130. pll control register 2 bit map 7 6 5 4 3 2 1 0 fs2_1 fs2_0 sel2 doub2 fs1 fs0 sel1 doub1 table 131. pll control register 2 bit descriptions bit name description fs2_[1:0] sample rate select for pll2. 00 = 48 khz. 01 = reserved. 10 = 32 khz. 11 = 44.1 khz. sel2 oversample ratio select for pll2. 0 = 256 f s . 1 = 384 f s . doub2 double-selected sample rate on pll2. 0 = disabled. 1 = enabled. fs[1:0] sample rate select for pll1. 00 = 48 khz. 01 = reserved. 10 = 32 khz. 11 = 44.1 khz. sel1 oversample ratio select for pll1. 0 = 256 f s . 1 = 384 f s . doub1 double-selected sample rate on pll1. 0 = disabled. 1 = enabled.
adav803 rev. a | page 55 of 60 internal clocking control register 1address 1110110 (0x76) table 132. internal clocking control register 1 bit map 7 6 5 4 3 2 1 0 dclk2 dclk1 dclk0 aclk2 aclk1 aclk0 iclk2_1 iclk2_0 table 133. internal clocking cont rol register 1 bit descriptions bit name description dclk[2:0] dac clock source select. 000 = xin. 001 = mclki. 010 = pllint1. 011 = pllint2. 100 = dir pll (512 f s ). 101 = dir pll (256 f s ). 110 = xin. 111 = xin. aclk[2:0] adc clock source select. 000 = xin. 001 = mclki. 010 = pllint1. 011 = pllint2. 100 = dir pll (512 f s ). 101 = dir pll (256 f s ). 110 = xin. 111 = xin. iclk2_[1:0] source selector for internal clock iclk2. 00 = xin. 01 = mclki. 10 = pllint1. 11 = pllint2. internal clocking control register 2address 1110111 (0x77) table 134. internal clocking control register 2 bit map 7 6 5 4 3 2 1 0 reserved reserved reserved iclk1_1 iclk1_0 pll2int1 pll2int0 pll1int table 135. internal clocking cont rol register 2 bit descriptions bit name description iclk1_[1:0] source selector for internal clock iclk1. 00 = xin. 01 = mclki. 10 = pllint1. 11 = pllint2. pll2int[1:0] pll2 internal selector (see figure 38 ). 00 = fs2. 01 = fs2/2. 10 = fs3. 11 = fs3/2. pll1int pll1 internal selector. 0 = fs1. 1 = fs1/2.
adav803 rev. a | page 56 of 60 pll clock source registeraddress 1111000 (0x78) table 136. pll clock source register bit map 7 6 5 4 3 2 1 0 pll2_source pll1_source reserved reserved reserved reserved reserved reserved table 137. pll clock source register bit descriptions bit name description pll2_source selects the clock source for pll2. 0 = xin. 1 = mclki. pll1_source selects the clock source for pll1. 0 = xin. 1 = mclki pll output enableaddress 1111010 (0x7a) table 138. pll output enable register bit map 7 6 5 4 3 2 1 0 reserved reserved dirinpd dirin_pin reserved sysclk1 sysclk2 sysclk3 table 139. pll output enable register bit descriptions bit name description dirinpd this bit powers down the s/pdif receiver. 0 = normal. 1 = power-down. dirin_pin this bit determines the input levels of the dirin pin. 0 = dirin accepts input signals down to 200 mv according to aes3 requirements. 1 = dirin accepts input signals as defined in the specifications section. sysclk1 enables the sysclk1 output. 0 = enabled. 1 = disabled. sysclk2 enables the sysclk2 output. 0 = enabled. 1 = disabled. sysclk3 enables the sysclk3 output. 0 = enabled. 1 = disabled.
adav803 rev. a | page 57 of 60 alc control register 1address 1111011 (0x7b) table 140. alc control register 1 bit map 7 6 5 4 3 2 1 0 fssel1 fssel0 gaincntr1 gaincntr0 recmode1 recmode0 limdet alcen table 141. alc control register 1 bit descriptions bit name description fssel[1:0] these bits should equal the sample rate of the adc. 00 = 96 khz. 01 = 48 khz. 10 = 32 khz. 11 = reserved. gaincntr[1:0] these bits determine the limit of the counter used in limited recovery mode. 00 = 3. 01 = 7. 10 = 15. 11 = 31. recmode[1:0] these bits determine which reco very mode is used by the alc section. 00 = no recovery. 01 = normal recovery. 10 = limited recovery. 11 = reserved. limdet these bits limit detect mode. 0 = alc is used when either channel exceeds the set limit. 1 = alc is used only when both channels exceed the set limit. alcen these bits enable alc. 0 = disable alc. 1 = enable alc.
adav803 rev. a | page 58 of 60 alc control register 2 address = 1111100 (0x7c) table 142. alc control register 2 bit map 7 6 5 4 3 2 1 0 reserved recth1 recth0 atkth1 atkth0 rectime1 rectime0 atktime table 143. alc control register 2 bit descriptions bit name description recth[1:0] recovery threshold. 00 = ?2 db. 01 = ?3 db. 10 = ?4 db. 11 = ?6 db. atkth[1:0] attack threshold. 00 = 0 db. 01 = ?1 db. 10 = ?2 db. 11 = ?4 db. rectime[1:0] recovery time selection. 00 = 32 ms. 01 = 64 ms. 10 = 128 ms. 11 = 256 ms. atktime attack timer selection. 0 = 1 ms. 1 = 4 ms. alc control register 3address 1111101 (0x7d) table 144. alc control register 3 bit map 7 6 5 4 3 2 1 0 alc reset alc reset alc reset alc reset alc reset alc reset alc reset alc reset table 145. alc control register 3 bit description bit name description alc reset a write to this register restarts the alc operation. the value written to this register is irrelevant. a read from this register gives the gain reduction factor.
adav803 rev. a | page 59 of 60 layout considerations getting the best performance from the adav803 requires a careful layout of the printed circuit board (pcb). using separate analog and digital ground planes is recommended, because these give the currents a low resistance path back to the power supplies. the ground planes should be connected in only one place, usually under the adav803, to prevent ground loops. the analog and digital supply pins should be decoupled to their respective ground pins with a 10 f to 47 f tantalum capacitor and a 0.1 f ceramic capacitor. these capacitors should be placed as close as possible to the supply pins. adc the adc uses a switch capacitor input stage and is, therefore, particularly sensitive to digital noise. sources of noise, such as plls or clocks, should not be routed close to the adc section. the capxn and capxp pins form a charge reservoir for the switched capacitor section of the adc, so keeping these nodes electrically quiet is a key factor in ensuring good performance. the capacitors connected to these pins should be of good quality, either npo or cog, and should be placed as close as possible to capxn and capxp. dac the dac requires an analog filter to filter out-of-band noise from the analog output. a third-order bessel filter is recommended, although the filter to use depends on the requirements of the application. pll the pll can be used to generate digital clocks, either for use internally or to clock external circuitry. because every clock is a potential source of noise, care should be taken when using the pll. the adav803s pll outputs can be enabled or disabled, as required. if the pll clocks are not required by external circuitry, it is recommended that the outputs be disabled. to reduce cross-coupling between clocks, a digital ground trace can be routed on either side of the pll clock signal, if required. the pll has its own power supply pins. to get the best performance from the pll and from the rest of the adav803, it is recommended that a separate analog supply be used. where this is not possible, the user must decide whether to connect the pll supply to the analog (avdd) or digital (dvdd) supply. connecting the pll supply to avdd gives the best jitter performance, but can degrade the performance of the adc and dac sections slightly due to the increased digital noise created on the avdd by the pll. connecting the pll supply to dvdd keeps digital noise away from the analog supply, but the jitter specifications might be reduced depending on the quality of the digital supply. using the layout recommendations described in this section helps to reduce these effects. reset and power-down considerations when the adav803 is held in reset by bringing the reset pin low, a number of circuit blocks remain powered up. for example, the crystal oscillator circuit based around the xin and xout pins is still active, so that a stable clock source is available when the adav803 is taken out of reset. in addi- tion, the vco associated with the s/pdif receiver is active so that the receiver locks to the incoming s/pdif stream in the shortest possible time. where power consumption is a concern, the individual blocks of the adav803 can be powered down via the control registers to gain significant power savings. table 146 shows typical power savings when using the power-down bits in the control registers. table 146. typical power requirements operating mode av dd (ma) dv dd (ma) odv dd (ma) dir_v dd (ma) power (mw) normal 50 25 5 5 280.5 reset low 30 4 2.5 1 123.75 power- down bits 12 0.1 1.3 0.7 46.53
adav803 rev. a | page 60 of 60 outline dimensions compliant to jedec standards ms-026-bcd 051706-a top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 11.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 0 . 1 5 0 . 0 5 7 3.5 0 figure 55. 64-lead low profile quad flat package [lqfp] (st-64-2) dimensions shown in millimeters ordering guide model temperature range control interface dac outputs package description package option adav803astz 1 ?40c to +85c i 2 c single-ended 64-lead low profile quad flat package [lqfp] st-64-2 adav803astz-reel 1 ?40c to +85c i 2 c single-ended 64-lead low profile quad flat package [lqfp] st-64-2 EVAL-ADAV803EBZ 1 evaluation board 1 z = rohs compliant part. purchase of licensed i2c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. ?2004C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04756-0-7/07(a)

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